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This page contains links to recently created documents, as well as
links to updated pages within this site. Re-visit
this page to find new documents as they are made.
Dec 2001
Feb 2001
- "
A 1.75-GHz Highly-Integrated Narrow-Band CMOS Transmitter with Harmonic-
Rejection Mixers,"
J.Weldon, J.Rudell, L.Lin, R.Narayanswami, M.Otsuka, S.Dedieu, L.Tee, K.
Tsai, C.Lee and P.Gray
Presentation for the 2001 International Solid State Circuits Conference
Feb. 6th, 2001
Dec 2000
- N. Sneed, "
A 2-GHz CMOS LC-Tuned VCO using Switched-Capacitors to Compensate
for Bond Wire Inductance Variation,"
(PDF) MS Thesis, University of California, Berkeley, Dec 2000.
- G. Desjardins,
"Adapative Digital Signal Processing Algorithms for
Image-Rejection Mixer Self-Calibration,"
(PDF) MS Thesis, University of California, Berkeley, Dec 2000.
Nov 2000
Feb 2000
- G. Chien, P.R. Gray,
"
A 900-MHz Local Oscillator using a DLL-based Frequency Multiplier
Technique for PCS Applications," (PDF)
Digest of Technical Papers, International Solid-State Circuits
Conference, San Francisco, CA. Feb. 8, 2000
- L. Lin, L. Tee, P.R. Gray"
A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using
a Wideband PLL Architecture," (PDF)
Digest of Technical Papers, International Solid-State Circuits
Conference, San Francisco, CA. Feb. 8, 2000
Jan 2000
May 1999
- A. Abo,
"Design for Reliability of Low-voltage, Switched-capacitor
Circuits," (PDF 635kB)
PhD Thesis, University of California, Berkeley, May, 1999.
Available as ERL Memo M99/25.
- A. Abo, P. R. Gray,
"A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,"
(PDF)
IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999.
- A. Abo,
"Preliminary Design of a 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline ADC,"
(PDF)
July 1998
- J.C. Rudell, J.J. Ou, R. S. Narayanaswami, G. Chien, J.A. Weldon,
L. Lin, K.C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson,
D. Gerna, M. Otsuka, and P. R. Gray,
"
Recent Developments in High Integration Multi-Standard CMOS
Transceivers for Personal Communication Systems ,"(PDF)
Invited paper at the 1998 International Symposium on Low Power
Electronics, Monterey, California.
June 1998
- A. Abo, P. R. Gray,
"A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter,"
(PDF-paper)
1998 Symposium on VLSI Circuits, Honolulu, June 1998.
- A. Abo, Paul R. Gray,
"A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter,"
(PDF/GIF/MIF/PS-slides) 1998 Symposium on VLSI Circuits,
June, 1998.
- C. J. Barrett,
"Low-Power Decimation Filter Design
for Multi-Standard Transceiver Applications," (PDF) UC Berkeley
MS Thesis, December 1997.
- R. S. Narayanaswami,
"The Design of a 1.9GHz 250mW CMOS Power Amplifier For DECT" (HTML)
(PS,
PDF), UC Berkeley
MS Thesis, May 1998.
April 1998
February 1997
- RF Short Course,
ISSCC, San Francisco, Feb 1997.
- Slides for "
A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless
Telephone Applications," J.Rudell, JJ. Ou, T.Cho, G.Chien, F.Brianti, J.Weldon,
and P.Gray. Presentation for the 1997 International Solid-State Circuits Conference
(GIF/MIF/PS) Feb. 8th, 1997
- Digest paper for "
A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless
Telephone Applications," J.Rudell, JJ. Ou, T.Cho, G.Chien, F.Brianti, J.Weldon,
and P.Gray. 1997 International Solid-State Circuits Conference
(GIF/MIF/PS) Feb. 8th, 1997
September 1996
- T. Cho, G. Chien, F. Brianti and P. R. Gray,
"A Power-Optimized CMOS Baseband Channel Filter and ADC for
Cordless Applications" (GIF/MIF/PS)
VLSI Circuit Conference Digest 96, June 1996.
- T.Cho, J.Rudell, P. R. Gray, et al,
"
A Multi-Standard Monolithic CMOS RF Transceiver
(Overview / Status),"
(HTML/MIF/PS) June 16, 1996.
- J. Rudell, G. Chien, J. Weldon, C. Barrett, L. Lin, M. Tsai, L. Tee,
M. Sabatini, and P. R. Gray,
"
Second Generation Multi-Standard Monolithic CMOS RF Transceiver,"
(HTML/MIF/PS) June 16, 1996.
- L. Lin,
"Design Techniques for Parallel Pipelined ADC", (PS),
UC Berkeley MS Thesis, May 1996.
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Last modified: Fri Jan 18 21:36:33 PST 2002