High-Speed Low-Power Sigma-Delta Modulators for Digital Wireless 
Communications Systems

Arnold Feldman

(Professors Paul Gray and Bernhard Boser)




Current implementations of digital portable communication system receivers 
use analog filters to select the desired channel followed by a Nyquist rate analog-to-
digital converter (ADC). To achieve greater progammability in a multi-standard 
receiver, it would attractive to select the desired channel in the digital domain. To 
remove the analog channel-selection filtering entirely would require a wide dynamic 
range ADC, such as a sigma-delta modulator. The oversampled ADC would digitize 
both the desired and undesired channels and remove the undesired channels using a 
digital decimation filter. An additional benefit of a wide dynamic range ADC is the 
reduction of AGC requirements in the receive path.

The goal of this work is the realization of a sigma-delta modulator to meet the 
requirements of a wireless receiver with wideband channels: 14 bits at 2 MS/s and 
minimum power dissipation using a 3.3 V supply. To reduce the power dissipation of a 
high-speed modulator, the oversampling ratio must made as low as possible. At an 
oversampling ratio of 16, a cascade architecture using three second-order modulators 
(2-2-2 cascade) will achieve 14 bit resolution. The architecture is sensitive to component 
mismatches which requires calibration of the first interstage gain to achieve 14 bit 
resolution; calibration can be done digitally using the LMS algorithm.

Both system and circuit level techniques are required to reduce power 
dissipation. At the system level, internal signals throughout the cascade are scaled to 
maximize the dynamic range at the output of each integrator. Similar to a pipeline 
ADC, capacitors may be scaled to the minimum value set by kT/C noise considerations 
at each stage in the cascade. Circuit level approaches include the use of a two-stage rail-
to-rail operational amplifiers optimized for minimum power dissipation.

Current work focuses on circuit design of the analog portions of the sigma-delta 
modulator for fabrication in the spring of 1996.