Yun Chiu
Dr. Chiu earned his Ph.D. degree from the EECS department at University of California, Berkeley in 2004. His research advisor was Prof. Paul Gray. He has recently joined the faculty of the ECE department at University of Illinois, Urbana-Champaign. Click this to visit his new website.
Thesis Papers Slides Patent Projects
Y. Chiu, "High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS," (PDF 1.1MB) PhD Thesis, 2004.
Y. Chiu, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.
Y. Chiu, P. R. Gray, and B. Nikolic, "A 1.8V 14b 10MS/s pipelined ADC in 0.18mm CMOS with 99dB SFDR," IEEE International Solid-State Circuits Conference, ISSCC'04, Digest of Technical Papers, San Francisco, CA, Feb. 14-19, 2004. pp. 458-459, 539.
Recipient of the ISSCC'04 Jack Kilby Outstanding Student Paper Award
Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems I, special issue of Advances on Analog-to-Digital and Digital-to-Analog Converters, vol. 51, pp. 38-46, Jan. 2004.
Y. Chiu, "Inherently linear capacitor error-averaging techniques for pipelined A/D conversion," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 229-232, March 2000.
Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband electronic linearizer for externally modulated analog fiber-optic links," IEEE Journal of Photonics Technology Letters, vol. 11, pp. 48-50, Jan. 1999.
Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband linearization of externally modulated fiber-optic links," IEEE International Topical Meeting on Microwave Photonics, MWP'98, Technical Digest, Princeton, NJ, Oct. 12-14, 1998. pp. 49-50.
Y. Chiu, P. R. Gray, and B. Nikolic, “A 1.8-V, 14-b, 12-MS/s Pipelined ADC in 0.18-um CMOS with 103-dB SFDR,” presented at the 2004 IEEE International Solid-State Circuits Conference, February 2004; html
Y. Chiu, “High-Performance Analog-Digital Interface Circuits in Deep-Submicron CMOS,” presented at the 2002 Intel PhD Forum, October 2002; PDF
Y. Chiu, “A High-Speed High-Resolution Pipelined A/D Conversion Technique - Interleaved Passive Capacitor Error-Averaging,” internal review, July 2000; PDF
Y. Chiu, B. Jalali, S. Garner, and W. Steier, "Broadband Linearization of Externally Modulated Fiber-Optic Links,” presented at the 1998 IEEE International Topical Meeting on Microwave Photonics (MWP ‘98), October 1998. PDF
Y. Chiu, "Improved CMOS Gain-Boosting Scheme using Pole Isolation Technique," U.S. patent No. 6,177,838.
Posted Simulink files may only work with Matlab R11 release. Please don't ask me questions.
EE290S project, "LMS Adaptive Digital Background Calibration of Pipelined A/D Converters," Fall 2001;
EE247 project, "A Study of Folding and Interpolating ADC," Fall 2000; Report (PDF) Slides (PPT)
EE225C project, "OFDM Receiver Design," Fall 2000 (later quoted by The MathWorks Inc., Educational resources of DSP and Communications Design); Report (PDF) Slides (PPT) Files(ZIP)
EE240 project, "A Gain-Boosted 90-dB Dynamic Range Fast Settling OTA with 7.8-mW Power Consumption," Spring 2000; Report (PDF)
EE231 project, "Simplified analytical equations incorporating finite source resistance to estimate switch induced error in Sample and hold circuits," Spring 2000. Report (PDF) Slides (PPT)