The expanding market for radio-frequency personal communication devices has led to the proliferation of different communication standards and a high consumer demand for low cost, low power, small form factor devices. As a result, present research focuses on the design of a monolithic receiver that can adapt to the various communications standards in a cost-effective CMOS technology.
A fully integrated receiver architecture necessitates the elimination of discrete high-Q image-rejection and IF filters. The received signal spectrum is typically downconverted to baseband or low-IF in its entirety. Because there is no channel filtering before the baseband blocks, both the desired signal and strong adjacent channel blockers may be present.
Consequently, the challenge of designing baseband circuits for integrated receivers is to realize the required analog functions for a variety of signal conditions. The baseband blocks of integrated receivers typically have very high dynamic range requirements.
This work focuses on the gain stage and anti-alias filter that precede the sampled data circuits or analog-to-digital converters in the baseband of an integrated receiver. In particular, this project explores the issues of designing low-power, high dynamic range baseband circuits for multi-standard applications.
The variable gain stage is designed to accomodate the gain variation in the RF front-end and maximize the input to the sampled data circuits. The 3-rd order filter is designed by combining an RC network and a second-order Sallen-and-Key configuration. This variable gain stage and filter will be used in the wideband IF with double conversion receiver architecture and is designed to meet the baseband signal conditions required of both the Digital Enhanced Cordless Telecommunications (DECT) and cellular (GSM,PCS-1900,DCS-1800) standards. Both the gain stage and filter are being designed in a 0.35 µm double-poly CMOS process and runs off a 3.3 V supply.