A 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter

University of California, Berkeley

Abstract

For portable DSP systems which require video-rate 8-10 bit ADC's, low power consumption of the ADC is one of the key requirements due to limited power supply from batteries. Also, as digital IC's operate at lower voltage, typically less than 5V, to reduce power consumption, the analog circuits also need to be designed for low voltage to be integrated on the same chip. This paper describes a 10-bit, 20-MS/s, 3mW pipeline ADC realized in 1.2-m CMOS technology. The converter is implemented in fully differential circuits and optimized to achieve low power consumption. It operates at 3.3 V to be compatible with low voltage digital IC circuits. It achieves a signal-to-noise-and-distortion-ratio (SNDR) of 58.7 dB, and its active area occupies 3.2 x 3.3 mm.

I. Architecture

A block diagram of a typical pipeline ADC is shown in figure 1. It consists of a cascade of N identical stages, and each stage is implemented by using a switched capacitor circuit and a low resolution flash ADC section. When the input signal is applied, each stage samples and quantizes the signal to its stage resolution of B bits, subtracts the quan

II. Power Reduction Strategies

In order to reduce the power dissipation of the ADC, four things have been done: (a) operating the ADC at low voltage, (b) using small sampling capacitors, (c) implementing the flash ADC with dynamic latches to avoid static power dissipation, and (d) scaling stages along the pipeline to the given resolution.

A. Low Voltage Operation

In order to operate the ADC at 3.3 V, a new op amp, which is used to implement the interstage amplifier, has been designed, and it is shown in figure 2. The op amp topology is a two stage configuration with a low-gain first stage to increase the effective transconductance (gm) of the amplifier. In addition, a gain-boost amplifier is used on the second stage PMOS current source to increase the output resistance. The dc level is self-biased by closing switches, sw1 and sw2, during sampling phase of the amplifier.

At low power supply voltages, MOS transmission gates do not function properly due to insufficient gate voltage to turn on the inversion layer in the channel. Therefore, in order to solve this problem, a charge pump circuit[3] has been designed as shown in figure 3a. By applying a square wave input signal of 3.3 V, C1 and C2 are self-charged to ~3.3 V, and an inverted square wave output of ~5 V is generated. By doing this, enough gate voltage can be generated to turn on the transistor. In this ADC, because the gate voltage overdrive is much higher than the signal common-mode voltage,

sampling switches are implemented with NMOS switches only

B. Minimum Size Sampling Capacitors

A fundamental noise source present in ADC's is thermal noise, and the magnitude of this noise is a function of the sampling capacitor size (~ kT/C). In order to reduce the power dissipation, the sampling capacitor must be reduced, since it becomes the load capacitance of the previous stage. Therefore, the size of the sampling capacitor is reduced until it is limited by this noise floor. However, small capacitors do not match well to high accuracy, and trim capacitor arrays are used to calibrate the DAC in a similar manner to [3].

C. Dynamic Comparators

In pipeline ADC's, since one extra bit is resolved in each stage, a large comparator offset can be tolerated, and no precision comparators are needed, which often require a pre-amp with dc bias current. Therefore, in this ADC, simple dynamic latches are used to implement the comparator in low resolution flash ADC to remove dc power dissipation, as shown in figure 4. In this comparator, the decision level can be set by changing the ratio of the input transistor widths (W/W), and no sampling capacitors are required. For one-bit per stage scheme, only two comparators are needed, and the offset of 250mV can be corrected for Vref = 1V.

D. Scaling of Stages Down the Pipeline

In general, in pipeline ADC's, since the stage resolution decreases down the pipeline, the stage requirements on the speed and accuracy become less stringent. Therefore, instead of using identical stages, stages in the later part of the pipeline can be scaled down. In figure 5, normalized op amp bias currents of each stage are shown. Near the front end, the sizes of sampling capacitors and operational amplifiers are determined by the noise floor, and toward the end of the pipeline, settling time of the op amp determines the size of each stage. By doing this, ~50% of dc power consumption can be reduced, since the operational amplifier can be made small in later stages.

III. Experimental Results

The ADC has been fabricated in a 1.2-m, double-poly, double-metal CMOS technology, and its active area occupies 3.2 x 3.3 mm. A chip photo is shown in figure 9.

In figure 6, SNDR is plotted for 1 MHz and 10 MHz input frequencies at 20-MS/s conversion rate. The peak SNDR is 58.7dB for 1 MHz input sine wave, which is higher than that of 0.8-m ADC described in [4]. In figure 7, differential nonlinearity (DNL) and integral nonlinearity (INL) vs. input code is plotted. The magnitude of the maximum DNL and INL are 0.5 LSB and 0.6 LSB, respectively.

Figure 8 shows the measured power consumption vs. the sampling frequency on a log-log scale. The op amp bias current is controlled by one master bias current source. At reduced bias current and a sampling frequency of 1 MS/s, the power consumption was 2.8 mW with SNDR of 58 dB.

VI. Summary

This paper describes a 10-bit, 20-MS/s, 35-mW pipeline ADC in 1.2-m CMOS technology, and its performance is summarized in Table I. The key features of this ADC are: new low voltage opamp, charge pump circuits for switches, careful scaling down of pipeline stages, 1 bit/stage architecture which allows usage of dynamic comparators, and small capacitors as set by kT/C limit with trim arrays for calibration. This shows that low voltage, low power operation of pipeline ADC can be achieved for video-rate applications.

References

[1] S. H. Lewis, H. S. Fetterman, George F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "10-b 20-MSample/s Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 27, pp.351-358, March 1992.

[2] Y.-M. Lin, B.Kim, and P.R. Gray, "A 13-b 2.5MHz self-calibrated pipelined A/D converter in 3-m CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Apr. 1991.

[3] Y. Nakagome et al., "Experimental 1.5-V 64-Mb DRAM," IEEE J. Solid-State Circuits, vol. 26, pp. 465-472, Apr. 1991.

[4] K. Kusumoto, K. Murata, A. Matsuzawa, S. Tada, M. Maruyama, K. Oka, H. Konishi,"A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC," in ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 1993.