A novel idea of a floating gate programmable MOSFET has been proposed. It uses a standard double poly CMOS process and Fowler-Nordheim tunneling concept to generate trapped charges in the floating gate, hence, vary the threshold voltage of the MOSFET. Preliminary results have been obtained through calculations and simulations for two readily available CMOS processes and some possible applications are discussed.
Floating gate MOS transistors currently receive a widespread use commercially as the data storage element in EPROM and EEPROM circuit. A typical example of a floating gate transistor is shown in Figure
1
.) In current binary applications, information storage is achieved by depositing large amounts of charge on the floating gate or by effectively removing this charge from the floating gate. These devices can be manufacture quite reliably and compact as indicated by the availability of megabit flash memory today.
The floating gate transistors have received little/minimal attention as an analog circuit element. However, there are unique applications for these devices in an analog circuit. As the trend of integrated circuits moves toward low power and low voltage, the floating gate transistor might find its way into the world of analog integrated circuit. For example, with traditional 5V power supply, the on resistance of a switch is relatively small. When you decrease the supply voltage, the on resistance increases due to the loss in the gate drive. (shown in Figure2)
Taking the advantage of the thin oxide in the modern technology, we can make electrons tunnel through the oxide with some voltage. In order to preserve the normal circuit topology, the programming has to occur between the floating gate and a programming gate. In this device, poly1 is used as a floating gate and poly2 is used for programming, as well as controlling. Shown in Figure3 is a simplified diagram of a CMOS floating gate device. The difference of the CMOS floating gate transistors and the EEPROM-type transistors is that the electron tunneling happens in the oxide between poly1 and poly2 instead of gate oxide which preserves the gate oxide for analog circuit operation.
A simplified diagram of a floating gate transistor is shown in Figure4
and d denote the oxide thicknesses for gate oxide and oxide between poly1 and poly2 respectively. This device can be modeled with two capacitors in series. When a programming voltage, V
, is applied, electric fields are found in both oxide layers. They are as follows:
where the ratios of the poly1 and poly2 overlap areas show up in the denominator. The current density of Fowler-Nordheim tunneling follows the equation
where A and E
are process-dependent constants and E is the electric field in the oxide.
In order to have the electron tunneling occur between poly1 and poly2, J needs to be much greater than J. From Equation3, this means E needs to be greater than E. From the Equation1 and Equation2, it is clear that A has to be much smaller than A to generate high electric field between two poly gates; hence C needs to be greater than C.
When the circuit is in operating mode, the same simplified device diagram and the two-capacitor model can be used. (Figure4) When a gate voltage, V
, is applied on the top gate, a capacitive divider divides the gate voltage by the geometric ratio of the capacitors. In order to turn the transistor on, V needs to be greater than the threshold voltage. Because of the capacitive divider, V needs to be significantly greater than V. However, a more effective device operation might be to make C much greater than C in order to have most of the V voltage drop across V.
To reiterate, for efficient programming, C needs to be greater than C. For efficient device operation, C needs to be greater than C. These two statements contradict with each other, is there an optimum for C and C? or is there other solution?
in the programming mode. The overlapping capacitance is generally much less than the gate capacitance, therefore, the efficient programming criterion is met. On the right, a poly-poly capacitor becomes C in the operation mode; and this capacitance is generally larger than the gate capacitance. Hence, the efficient operation mode criterion is also met.
The side view shows a cross-section view of the layout from the center of the gate area. The region where the small poly2 stub overlaps poly1 is where the electron tunneling occurs. It is believed that the electric field at the corner and edge of poly2 is highest. Also notice that poly1 layer is not connected to any nodes in the circuit in this design; hence is given the name `floating gate'.
To put these concepts and equation into real examples, two typical CMOS processes are chosen for the simulation. A less aggressive technology used as an example is the MOSIS 2
m DPDM (Double Poly Double Metal) CMOS Process. A more modern technology example used is the TSMC 0.6m DPTM (Double Poly Triple Metal) CMOS Process. The results are shown in the next two sections.
6 shows the relationship between final change in threshold voltage as a function of programming voltage. A linear dependence is shown, which matches with the analytical result as well as the intuition. As the programming voltage increases, the electric field across the oxide increases as well. More electrons will be either deposited or removed from the floating gate, hence a greater change in the threshold voltage.
The current density follows a strong exponential curve (shown in Figure7), decreases sharply below certain voltage, in this case, the voltage is roughly 6 volts. The fact that the current density drops sharply below 6 volts shows that Fowler-Nordheim tunneling doesn't occur for low voltages. Hence, during normal circuit operation (Vdd < 5V), the transistors are safe. Furthermore, in normal circuit topology, no floating gates are designed to store charges, therefore, all charges are dissipated through the supplies.
2. TSMC 0.6m DPTM CMOS Process
m CMOS process, the oxide thickness is noticeably smaller than the previous example. And the process threshold voltage is also significantly lower than the MOSIS 2.0m process. The results of the same experiment done for the example are shown in Figure8 and Figure9. They both follow the analysis describes earlier with linear dependency of threshold voltage change with programming voltage and strong exponential function for the current density vs. programming voltage.
Please note that the numerical values for the current density appear to be incorrect due to the lack of information on the Fowler Nordheim equation. The values used in the calculations for the constant A and the E are obtained for a different process, they are process dependant parameters.
In conclusion, a floating gate, programmable MOSFET transistor using standard CMOS process has been proposed. It does not require special process to achieve the Fowler-Nordheim electron tunneling. Possible applications might be for low power/low voltage design, to replace MOS switches in low voltage design, to replace fuse trimming technology and capable to be reversible, etc. Preliminary results are shown. The charge retention performance is believed to be at least as good as the EEPROM technology because of the layer of SiO surrounding the floating polysilicon gate. The programming speed is not an issue in this design since this device doesn't need to be programmed very often. The author believes that this is a novel idea, the value of this device is yet to be determined. The actual functionality of the device can only be tested with fabricated wafers.
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