CHAPTER 1 Introduction

1.1 Motivation and Goal

1.2 Thesis Organization

CHAPTER 2 Pipelined Analog-to-Digital Architecture

2.1 Overview

2.2 Evolution of Pipelined A/D Architecture

2.2.1 Flash Architecture

2.2.2 2-step Flash Architecture

2.2.3 Conventional Pipelined A/D Architecture

2.3 Power-Optimized Pipelined A/D Architecture

2.3.1 Power-Optimized Per-Stage Resolution

2.3.2 Power-Optimized Capacitor Scaling

2.3.3 Digital Correction

2.4 Summary

CHAPTER 3 Circuit Techniques for Low Power, High Speed Pipelined A/D

3.1 Overview

3.2 Low Power Techniques

3.2.1 Dynamic Comparators

3.2.2 Capacitor Scaling

3.3 Low Voltage Techniques

3.3.1 2-stage 3.3V OpAmp

3.3.2 Low Voltage SC Circuits

3.4 Digital Correction Circuit

3.5 Bias Circuits and Clock Generation

3.6 Summary

CHAPTER 4 Experimenta Prototype and Measurement Results

4.1 Prototype

4.2 Experimental Results

4.3 Integrated A/D with DECT receiver

4.4 Summary

CHAPTER 5 Conclusion

5.1 Conclusion

5.2 Power Comparison

5.2.1 Digital Section

5.2.2 kT/C Limited Power Comparison

5.2.3 Parasitic Limited Power Comparison

5.2.4 Conclusion

Appendix A Reference Voltage Generator

A.1 Introduction

A.2 Resistor String Voltage Reference Generator

A.3 Capacitor Array Reference Voltage Generator

Appendix B MOS Sampling Circuits

B.1 Introduction

B.2 Finite Bandwidth

B.3 Charge Injection

B.4 Clock Feedthrough

Appendix C Nonidealities in SC Circuit

C.1 Introduction

C.2 Finite Open Loop Gain

C.3 Noise Contributors in SC Circuit

C.4 Total Input-Referred Noise

References