CHAPTER 4

Experiment Prototype and Measurement Results

4.1 Prototype

A prototype of the pipeline A/D converter is designed and fabricated in 0.6m CMOS DPTM process. The architecture used is described in Section 2.3 with nine pipeline stages where the last stage is only a pair of comparators. The sizes of beginning stages are scaled according to the noise limitation for optimum power and later stages are scaled to meet the speed requirement of the converter. The SC circuit in the first three stages also contains digital calibration, in essence, small capacitors are digitally switched between the sampling and feedback capacitor to compensate for capacitor mismatches. A die photo is shown in Figure 4.1. The active area is measured 1.2m x 1.2m shown on the right hand side of the die photo ( Figure 4.1). Since the die size is fixed for this fabrication run, extra digital circuitry is added on the left, along with some dummy metal lines for process yield purposes.

The floor plan of the layout is to place the first four stages on top and fold the last five stages to the bottom to minimize the wiring capacitance on the clock lines and form a square active area. The clock lines are routed in the center of the active area where the appropriate phases are tapped off at the location of each stage in the pipeline. Although the analog circuits are scaled down the pipeline, the digital section remains roughly the same size for all stages. It is apparent from the die photo that the analog section which is away from the center line is scaled down the pipeline; where as the digital section which is close to the center clock lines stays about the same size. Digital correction is at the lower left corner of the active area; and 10 bit output is produced at the pads on the bottom.

The prototype of the A/D converter is, instead of mounted in a conventional package, mounted on a printed circuit board with chip-on-board technology. This technology allows silicon dice to be attached directly onto a printed circuit board which has very fine bondwire landing pads (similar to the ones in conventional packages.) This technology greatly reduces the bondwire and lead inductance because the die can be placed extremely close to the pads.

4.2 Experimental Results

The chip is fabricated and a printed circuit board is produced using the chip-on-board technology (described in the previous section). Figure 4.2 shows the SNDR vs. Input level for 100kHz and 20MHz sine wave inputs sampled at 40MS/s. The peak SNDR is 58.8dB for 100kHz input. A degradation in higher input frequency is expected due to the fact that the first stage does not have a dedicated S/H to drive the first stage input capacitors and flash A/D. The flash A/D is triggered at four inverter delays after the input signal is sampled; for higher frequency input, the difference between the inputs sampled by the capacitor and flash A/D might be large, hence create a large nonlinearity. However, for some applications, the input to the A/D is a held SC circuit output (Section 4.3), S/H is not required.

Code Density Test shows the DNL and INL are within one LSB, shown in Figure 4.3. A layout error, associated with a leaking pn junction at a critical node, had been found in this design. Silicon microsurgery had been done to fix the error. Although the SNDR has improved to a 10-bit resolution at 40MS/s; for a slower sampling rate, the SNDR decreases. It is believed that some connections for later stages were not made with the silicon microsurgery (about 50 connections were required to fix the error). The large offset in the output codes might also be contributed by the layout error.

4.3 Integrated A/D with DECT receiver

As an example of high integration, in addition to the stand alone A/D chip, it is also integrated with a RF receiver chip which is currently under development in the research group. The simplified block diagram is shown in Figure 4.4.

Since the sampling rate is much slower, the settling requirement for each stage is relaxed. Therefore, the bias current for the active circuits can be scaled down to reduce the power consumption. Minor modifications need to be made to taylor the A/D to fit in the receiver chip. These include redesign on clock generator and re-routing of clock lines and output lines. Differential output with an attempt to minimize the noise injected into the substrate from the full CMOS logic swing is used. All the blocks shown in Figure 4.4 are implemented onto one single die including the ring oscillator based frequency synthesizer. The chip is currently under evaluation.

4.4 Summary

Experimental results for a 28mW 10b 40MS/s pipelined A/D converter is presented. Taking the advantage of scaled technology, the power dissipation and sampling rate of a pipelined converter have improved. The power comparison with some recent work is presented in