CHAPTER 5

Conclusion

5.1 Conclusion

A high speed, low power and low voltage A/D converter with scaled technology has been investigated here. A prototype which achieves 28mW 10b 40MS/s A/D is presented. It has also been demonstrated that CMOS A/D can be integrated with other circuit blocks in a large system. For that, the prototype is integrated with a monolithic CMOS RF receiver for DECT system.

The techniques which contribute to the goals of this research can be categorized into two sections. In architectural level, the choice of per-stage resolution, coding and digital correction relaxes the requirements on some active circuit blocks which are conventionally known as power hungry blocks. Capacitor scaling (i.e. pipeline scaling) minimizes the overdesign for later stages in the pipeline. In circuit level, taking advantage of digital correction, dynamic comparators are used to eliminate static power consumption. Capacitor scaling reduces the OpAmp sizes for later stages. A high speed, low voltage OpAmp with a pre-amplifier and cascode transconductance stage is used to achieve fast settling and high DC gain. Lastly, clock boosting circuit is used to reduce the on-resistance due to low supply voltage.

A prototype is built in 0.6m DPTM CMOS process and measured results are shown in Chapter 4. At conversion rate of 40MS/s, the A/D achieves a max SNDR of 58.5dB with 100kHz input. And DNL and INL curves show a good correspondence of the SNDR results.

In conclusion, having architectural and circuit techniques combined with scaled technology, a high speed, low power and low voltage A/D can be achieved. The next step will be to look into the effect of integrating such an A/D converter as a circuit building block in a larger system and how to deal with integration problems, such as substrate noise coupling, supply bounce, etc.

5.2 Power Comparison

As the CMOS technology scales to a smaller feature size, it is apparent that digital circuits will benefit from it in speed, power and area. These benefits can not be applied to analog circuits directly simply because the figures of merit in analog circuits extends beyond speed, power and area. Since the A/D converter is becoming a building block in a larger DSP or communication system, it is essential to study how the technology scaling will affect the performance of a mixed signal block, such as an A/D converter.

The comparison shown below will be between the 35mW 10b 20MS/s pipelined A/D converter in 1.2m CMOS process and the 28mW 10b 40MS/s pipelined A/D converter in 0.6m CMOS process. First, power savings in digital section due to technology scaling is examined. Following that is an attempt to compare the SC circuit when the performance is limited by noise. Lastly, a quick look at the SC circuit when parasitic capacitance is limiting the performance. In order to simplify the comparison, the sampling rate for the 0.6m example is first scaled to be 20MS/s (the same as the first case.) Then the effect of doubling the conversion rate will be discussed.

5.2.1 Digital Section

The digital section in this A/D design includes the clock generator, comparators, DAC logic and charge pump circuit. (in the 0.6m example, the digital correction circuit is also included.) The power dissipation for a digital circuit is generally described as

where is the clock rate of the circuit. For a given sampling rate and supply voltage, the power dissipation is only a function of capacitance (shown in equation above). Assume, to the first order, the ratio is the same for both designs, only for each device is required for the scaled process. Further assume that is increased rougly by a factor of 2, technology scaling makes the gate capacitance of that in the 1.2m version. (shown in equations below)

In addition to the gate capacitance, parasitics also play a very important role in power dissipation.

The effect of technology scaling on source/drain parasitic capacitance is not obviousbecause it depends on doping density, junction depth, source/drain area scaling, etc. If we assume that parasitics are only affected by the scaled feature size, the ratio of the source/drain parasitic capacitance between 1.2m and 0.6m process is roughly 2. Other sources of parasitics capacitance, such as wiring, overlapping, also change with technology. Although the line width of a metal line may decrease with technology, the coupling between two adjacent metal lines tend to increase because the minimum separation between metal lines are decreased. Other minor factors, such as metal resistance requirement, may determine the width for a long metal wire which will also affect the parasitic capacitance. In general, because the overall die size is about smaller, we can assume that the parasitic (if dominated by wiring and overlapping) is roughly .

In summary, the power saving for the digital section in an A/D converter running at the same sampling rate is roughly between and depending on the dominating factor between gate and parasitic capacitances. One good example is the clock generator circuit. For the same ratio, the gate capacitance in the scaled technology is about of the previous version. In addition, parasitic capacitance is roughly of the 1.2m version. Therefore, a power savings of to is expected for the scaled 0.6m process. In the lab, the power is measured to be xxmW for the 1.2mm case and 2.2mW for 0.6m case.

5.2.2 kT/C Limited Power Comparison

The power analysis for analog circuits is not quite as straight-forward as the digital circuits. Since the sampling capacitor in this design are scaled according to the noise requirement in the first few stages and settling requirement in the later stages, these two cases will be examined independently in the context of power dissipation with scaled technology.

In the 10-bit example, the capacitors in the first stage is determined by the noise limitation, therefore, the required capacitor size is the same in both technologies. For a fixed conversion rate, the required time constant would also be the same and it follows,

where

and

where is the load capacitance from the next stage.

Let's assume the and feedback factor, , stay roughly the same value because parasitic capacitances are generally insignificant in this OpAmp topology. To get the same , needs to be the same where it follows the equation

Assume stays the same for both technologies. If is increased by a factor of 2 and L is decreased by a factor of 2, W only needs to be of the previous design to maintain the same . From the second part of the above equation, it is obvious that will remain the same, hence the power dissipation is the same to the first order.

In the 1.2m design, a gain boost amplifier is used to compensate for the low output resistance on the PMOS transistors. The amplifier is eliminated in the 0.6m design because the output resistance performance is reasonably good. And by using longer channel devices, a sufficient output resistance can be achieved with the cascode PMOS current source. The power used in the gain boost amplifier was about 30% of the entire OpAmp. By eliminating it, the power dissipation is reduced significantly.

In reality, since is kept the same for noise reasons, is higher in the scaled technology for a particular bias condition and a fixed . This translates to an increase of speed with the same power dissipation. Furthermore, can also be lowered in the scaled technology to increase . Also if we re-examine the SC circuit more carefully and with the condition described in the previous paragraph, the parasitic capacitances for both the OpAmp input and source/drain output capacitances are smaller in the scaled technology than the 1.2mm design. This improves the feedback factor, as well as the settling time.

In conclusion, most of the power saving in the scaled technology comes from the elimination of the gain boost amplifier. Although the analysis above shows no power gain in the amplifier; in reality, higher sampling rate is achieved with roughly the same amount of power in the noise limited stages. The increase of feedback factor due to the reduced parasitics also improves the power dissipation. It's been shown that the power dissipation for the first pipelined stage is ~4.5mW for the 1.2m (20MS/s) case and ~3mW for the 0.6m (40MS/s) case. (a power saving of roughly 30%, mainly due to the elimination of the gain boost amplifier.)

5.2.3 Parasitic Limited Power Comparison

In the later stages of the pipeline, the limitation on the capacitor is no longer the noise, instead is determined by the parasitic capacitance. (i.e. the and need to be sufficiently larger than the parasitic to have a reasonable feedback factor.) By using an iterative method, the size of the OpAmp and capacitors are determined by the speed requirement of the A/D converter. If the A/D in both cases are running at the same speed, less parasitic capcitance, hence smaller capacitors and OpAmp, will contribute to lower power dissipation.

To achieve the same conversion rate, the same time constant is required for both cases. If the is determined by the parasitic capcitance, it is decreased by about a factor of 2 when the technology is scaled. The factor of 2 comes from the fact that the parasitic capacitance is dominated by the gate and source/drain capacitances in OpAmp's. And as described in the previous section, the capacitance for these is scaled by roughly a factor of 2 due to scaled geometries. This means can be scaled by a factor of 2 as well. If is kept constant for the OpAmp, the current required can be reduced by roughly a factor of 2, which translates to a power saving of .

In conclusion, the power savings of 2 is estimated for parasitic limited pipelined stages running at the same speed. However, the power of these stages is usually insignificant in comparison with the overall power dissipation of the A/D converter because of the capacitor scaling which was used in the design. In the 1.2mm example, the first stage power dissipation is ~4.5mW where the last stage only consumes ~0.5mW.

To summarize, since the line between the noise limited stage and parasitic limited stage is not clear, the power savings in analog circuit will be roughly less than . (in limiting case, power reduction is less than a factor of 2, mainly due to the increased and decreased ; and in parasitic limiting case, the power saving is roughly a factor of 2.) However, because the elimination of the gain boost amplifier with the scaled process, the 30% of power is reduced with no penalty.

5.2.4 Conclusion

In conclusion, although a power saving is intuitive with scaled technology, it is difficult to quantify the power saving factor in relation with the technology scaling factor. However, from the above discussion, power dissipation in digital section will improve between and ; where the analog section will improve by roughly for a given samlping rate. The measured power dissipations for both cases running at 20MS/s are 35mW for 1.2m and 17.4mW for 0.6m; of which about 50% of power is dissipated in digital circuits. A factor of 2 in power saving is observed with the scaled technology which was predicted earlier in this chapter.

When pushing the sampling rate to the limit of technology, the 1.2m achieves 20MS/s at 35mW, where as the 0.6m achieves 40MS/s at 28mW. Doubling the sampling rate will double the power dissipation in digital circuits; therefore, the power saving of factor is compensated for the higher speed. In analog circuit, no power saving is observed for doubling the sampling rate in the scaled technology; however, the elimination of gain boost amplifier reduces the power. Essentially, with a scaled technology, one can achieve a higher sampling rate with no power penalty.