fig 1: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
Comparison between analog motion estimator (B) and the standard one (A)
B/W Adaptive Image Grabber with Analog Motion Vector Estimator at 0.3 GOPS
Alfredo Tomasini, Maddalena Brattoli, Ernestina Chioffi, Gianluca Colli, Danilo Gerna, Marco Pasotti
Abstract
A chip with QCIF B/W CMOS camera and analog motion estimator using Block Matching Algorithm (BMA) has been developed. A full search algorithm is implemented with Reference Block (RB) of 8x8 pels and Search Window (SW) of 16x16pels is presented. A 0.7 µm CMOS technology has been used, with: PW <100mW @ 5V and computation speed of 0.3 GOPS and total size of 150 mm2.
Existing video coding standards, like H261 [2], MPEG-1&2 [3] are based on DPCM image compression scheme with Motion Compensation (MC) to reduce transmission bit-rate. MC is the most expensive block, and digital approaches normally require power of about a few hundred mW [5]. It could be proved that a precision reduction (0.4 dB in S/N) in BMA computation does not drastically affect the final quality, thus suggesting a parallel analog implementation saving a lot of power. A second expensive source of power consumption are the A/D and D/A conversions which can be reduce with a light variation of standard H261 scheme (fig 1). The modified scheme uses two Analog Memory (AM) to compare consecutive frames. Good performance in speed and power is obtained with a little loss (0.5 dB) on S/N ratio. A H261 compatible bit-stream can be produced to guarantee the interface with H261 decoders.
The chip (fig 2) contains a B/W CMOS Adaptive Video-camera (AV) providing QCIF (176x144 pels) [2] [4], two analog memories, a Motion Estimator (ME), and a small controller to synchronize the different computational phases .
In the acquisition phase the AV determines the average radiation value from which the storage time is estimated. The sensor cell contains a PN junction, a capacitance and three switches. The switches are used to download the photo current into a special AGC, or over the internal capacitance (fig 3). In the first phase all junctions are connect together to download the current inside AGC. It defines the integration time D t and switches the photo current over the internal cell capacitance for this amount of time. Thence a frame is grabbed inside the sensor. The third switch allows access to the charge stored into the cell, one line at a time. 176 charge amplifiers integrate this charge and provide an output voltage. A parallel to serial conversion generates a signal with a speed of 2.5 Msamp/sec. This analog signal are sent to AM.
AM's are addressable in input line per line. The incoming analog values are held on a bank of 176 capacitors at the nominal speed of 2.5 Msamp/sec (temporary S/H). At the same time, at the speed of 100 KHz, a second bank of capacitor, writes inside the memory cells their values, using 176 charge amplifiers (CA). A capacitance of 300 fF with a NMOS source follower constitutes the memory cells. During the writing phase a good precision is obtained putting the cells inside the feed-back loop of CA. This technique automatically compensates the threshold variations of NMOS and other parasitic effects (fig 4). RB memory stores the current frame, SW the previous one. The stored frames are read through an Analog port with 8 Analog values (AA8) at an equivalent speed of 6.4 Msamp/sec.
The ME starts the computation receiving the reference block RB and the SW from AM's. RB and the SW are transferred from the AM's , through two AA8 ports with a transfer rate of 12.8 Msamp/sec (transfer time: 38.4 m s/RB).
For each RB, ME looks for the matching block in a [-R,R] (R=4 pels) search range. It contains 64x81 cells, with a parabolic V/I transfer function [1]. ME loads analog values at the input of square cells, which transform differential input voltages into an output current. A special routing (fig. 5) allows to calculate in parallel the Euclidean distances between the 81 candidate blocks and the RB (fig. 6; eq. 1) ( 15KOP are performed at the same time[6]).
The ME chooses the minimum distance (current), and provides directly the vector address of the best matching block (fig. 6; eq 2).
The computation time is proportional with the best matching distance, and its maximum is 20 m s with equivalent computation power of 0.75 GOPS (MIN function excluded).
The AV is able to manage irradiance value of 0.5¸ 20 W/m2 ; it uses a PN junction of 338m m2, as active area, and a capacitance of 180fF as storage element; the total cell is 42x37m m2. An average responsivity of 0.11A/Wm2 has been measured (fig 3). Improve radiance range is possible tuning the current parameters of AGC circuit. The frame rate is limited by storage time, at the smaller storage time 90 fr/sec is achievable. A S/N of 35dB has been measured with an output range of 2.1 V. Total power consumption < 50mW@10MHz for a total amount @ 130 Kdevices.
The AM can read and write 60 Frame/sec with a power consumption of 8 mW and 130 Kdevices. The memory is characterized by a signal to noise ratio of 39 dB per frame, and 42 dB over windows of 16x16pels (SW) over a input/output range of 2.0V. A signal loss of @ 1/66 V/sec has been measured at 27.
The I/O communication channels for ME consist of two input analog port AA8, for an equivalent input rate of 12.8 Msamp/sec, and a digital 7 bit output port. An average computation speed of @ 22 Kvectors/sec is achieved using the standard access time at the two AM's. The power consumption of 8mW for a total amount of 60Kdevices. The performances validation of such device is directly given, by the S/N ratio on motion predicted vectors. The chip results are compared with the ideal estimator (fig 7).
Acknowledgments:
Special thanks to: A. Leone, A. Kramer and L. Fumagalli
References:
1 E. Seevinck, R. F. Wassenaar, "Journal of Solid-Sate circuits" Vol sc-22 , June 1987 pag 366-177
2 CCITT Video Coder for Audiovisual Services at px64kbit/s.
3 ISO/IEC 13818 2 "Coding of Moving Pictures and Associated Audio", Mar. '94.
4 ISO/IEC JTC1/SC29/WG11, March 1995 Doc. No. 95/093, "MPEG4: Short introduction and Demostration of H.263 including all options".
5 ISSCC95 M. Harrand et.al, "A Single Chip Videophone Encoder/Decoder".
6 F. Bellifemine, P. Garino, M. Marchiso: Cselt Italy, SPIE Vol 2451, "VLSI-driven System Analysis of the Motion Estimation process in MPEG-2 video".
Figures
fig 1: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
Comparison between analog motion estimator (B) and the standard one (A)
fig 2: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
System Block diagram.
fig 3: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti Sensor cells with timing and responsivity of single device
fig 4: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti Memory cells with schematic of charge amplifier and feed-back loop technique.
fig 5: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti (left) LE = Load Enhancement parallel v.s. serial access; (right) Redundancy reduction
I
k = K
k= 1 ... 81 eq ( 1)
(eq 2)
fig 6: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
Compuational equations
fig 7: Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
Signal to Noise ratio for a standard sequence and an internal one.
fig 8 Paper 6.2 - A. Tomasini, M. Brattoli, E. Chioffi, G. Colli, D. Gerna, M. Pasotti
Chip photo
Glossary
AGC Automatic Gain Control
AM Analog Memory
AV Adaptive Videocamera
BM Block Matching
CA Charge Amplifier
DPCM Digital Pulse Code Modulation
MC Motion Conpensation
ME Motion Estimator
MPEG Moving Picture Expert Group
MV Motion Vector
OPS Operation per Second
QCIF Quarter Common Interface Format
RB Reference Block