B/W Adaptive Image Grabber with Analog Motion Vector Estimator at 0.3 GOPS
SGS-Thomson Microelectronics
Alfredo Tomasini, Maddalena Brattoli, Ernestina Chioffi,
Gianluca Colli, Danilo Gerna, Marco Pasotti
Paper 6.2
Agenda
Targets of chip and technology
Chip block diagram & photo
Adaptive B/W image grabber
Analog Memory
2-D Block Matching Array
Hardware results & Testing setup
Summary & Conclusions
Targets
Technology: - CMOS 0.7µm (5V)
Design & architecture
Chip block diagram
System approaches to BMA in analog
Chip photo
B/W image grabber - architecture
Adaptive B/W image grabber QCIF format
B/W image grabber - cell circuitry
·
Phase 1 - readout global current µ scene luminance·
Phase 2 - current storage across capacitance (shutter)·
Phase 3 - readout the charge previously stored
B/W image grabber - cell architecture
·
Diode area 338 µm2·
Capacitance value 115 fF·
Cell voltage range 1.5V - 5V·
Rows S/N 35dB (no offset comp.); columns S/N 47dB
B/W image grabber - characteristics
·
Total device area 49 mm2 (130 k dev)·
Cell size 42x37 µm2 (fill factor 27%)·
Power 45 mW@5V (2.5Mpels/sec)·
Tunable luminance range 0.5 - 20 W/m2·
Frame rate luminance dependent 25fr/sec·
Signal to noise ratio 35dB ( » 6 bits)·
Output voltage range 4 - 1.8 V (analog)
Analog Memory - architecture
Store an entire frame 176x144 pels
Analog Memory - write-read circuit
·
Phase 1 - reset, off-set compensation and pre-sampling·
Phase 2 - writing memory cell through amplifier·
Phase 3 - readout the analog value open loop
Analog Memory - storage features
Leakage current measured on 300 fF vs. temperature
No limits on storage time for typical working conditions
Analog Memory - characteristics
·
Total device area 25 mm2 ( 130 K dev.)·
Cell size 21 x 22 µm2·
Power dissipation 6mW@5V (clock 2.5MHz)·
External addressable control·
Writing rate 2.5 Msamp/sec with analog multiplexing·
Reading rate is 800kHz (parallel 8 samples at the time)·
Signal to noise ratio 39 dB (» 6.5 bits)·
Input and output voltage range 2.0 V
Matching Block Algorithm - concept
BMA requirements
Limited low precision (6-7 bits)
High computation throughput
·
Low power is desirable for portable applications
2-D Block Matching Array - computation
Computational steps:
1.Differental Square Iout = Keq(VA - VB)2
2.Distance Summing Itot= K 
3.Minimun Distance Selection MIN
2-D Block Matching Array - differential square
Iout = Keq(VA - VB)
2
2-D Block Matching Array - distance summing
I
TOT = K
2-D Block Matching Array - minimum distance
step 3 Motion vector = MIN
j=1,...,81(Iou)j = MINj=1,...,81
Parallel comparison of the MB against 81 block of SW
2-D Block Matching Array - routing strategy
Simple and regular 2-D routing structure
2-D Block Matching Array - architecture
Parallel loading of SW and MB 8 pels at the time
2-D Block Matching Array - characteristics
·
Total Device Area 24 mm2 (70 Kdev)·
Matching block 8x8 pels Search window 16x16 pels·
Computing Rate is 21Kvectors/sec (0.7 GOPS)·
Total Power Dissipation is 8mW@ 5V·
Input pels rate 8 + 8 analog values at 800 Ksamp/s·
Input voltage range 2.0V·
PSNR on standard video sequence 37.3 dB (» 6 bits)
2-D Block Matching Array - hardware results
·
Transmission coder emulating 64 Kbit ISDN channel·
Precision limitations of analog approach of BMA has a little impact on PSNR
Testing scheme
Simple data acquisition system capture frame and motion vectors @ 5-10Fr/s
Testing setup
Summary & Conclusions
Advantage:
·
Multiple functions on a single chip (camera + frame memory + BMA)·
Low power (< 100mW@5V)·
New Architecture for analog BMA·
High parallelism for a full search algorithm (simple and regular architecture)
Drawback:
·
Low flexibility - dedicated "ASP"·
Low noise immunity·
Sensitivity to process variation·
Limited scalability