Keith's Home Page

My area of interest is in analog integrated circuits for high speed data communications. My research is part of InfoPad's RF project dealing with the downlink reception. A DS-CDMA demodulator prototype chip has been fabricated to demonstrate a passive analog integration technique that makes it possible to perform a high-speed correlation with minimal power. The prototype chip dissipates 75mW when operating at 128MHz. My advisor is Paul Gray at the University of California at Berkeley.

Papers

K. Onodera, P. Gray, "A 75-mW 128-MHz DS-CDMA Baseband Demodulator for High-Speed Wireless Applications", IEEE J. Solid-State Circuits, vol. 33, pp. 753-761, May 1998 (166k pdf)

K. Onodera, P. Gray, "A 75mW 128MHz DS-CDMA Baseband Correlator for High-Speed Wireless Applications", 1997 VLSI Circuit Symposium, June 1997 (31k pdf)

K. Onodera, A. Abo, "A Second-order Sigma Delta Modulator", May 1995 (186k pdf)

K. Onodera, S. Wu, "Power Reduction for High Speed Clocking" , May 1993. (mif/pdf)

Slides

K. Onodera, P. Gray "An Analog Based Binary Correlator for CDMA Systems" ,BWRC Dedication, Berkeley, CA, Jan 1999. (77k pdf)

K. Onodera, P. Gray "A 75mW 128MHz DS-CDMA Baseband Correlator for High-Speed Wireless Applications" ,1997 VLSI Circuit Symposium, Kyoto, Japan, June 1997. (69k pdf)

K. Onodera, "Low Power Analog Correlator" ,1994 ILP Conference, UC Berkeley, Feb 1994. (mif/pdf/gif)

K. Onodera, S. Wu, "Power Reduction for High Speed Clocking",May 1993. (mif/pdf/gif)

Thesis

Title: "Low Power Techniques for High-Speed Wireless Systems"

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Keith Onodera, Ph.D.
Email: keitho@ieee.org

finger keitho@aloha

Last modified: Wed Jul 20 08:37:09 PDT 2005