Robert Neff

At Berkeley I worked on CAD for Analog Circuits. In my Ph.D. project, I combined optimization with circuit simulation and analysis to create high performance Digital/Analog Converters, and tightly couple this with a layout routine which used cell stretching and tiling to create the final DAC. I completed my thesis in early 1995, and filed in April, 1995. Currently, I am doing analog IC design in the Mixed Signal Electronics Department at Agilent Labs, Agilent Technologies, Palo Alto, CA.

My dissertation and the DSYN (Dac SYNthesis) distribution are available for downloading:

Automatic Synthesis of CMOS Digital/Analog Converters (900k compressed postscript). 3 included layout plots are in this archive of postscript plots (240k compressed tar).
The DSYN distribution: Sun or Decstation version. (750k of compressed tar):

On an unrelated topic -- FAQ for Northern California Canoeing!

My advisor is Paul Gray at the University of California at Berkeley. The Berkeley Analog CAD Group also has a web page.

Back to the PRG Group page.

Layout of 8 bit, 100MHz DAC created with DSYN (100k gif file)

A Module Generator for Current Output CMOS Digital/Analog Converters. Slides used for the Industrial Liason Program on March 8, 1995. (1.1M postscript file)

CICC '95 submission describing synthesis process. (1.2M postscript file)

Slides from a CICC '95 talk describing DAC synthesis. (1.1M postscript file)

DSYN: A Module Generator for High Speed CMOS Current Output Digital/Analog Converters submitted to the Journal of Solid State Circuits for publication in March, '96. (170k postscript file)

Robert Neff

Agilent Technologies
3500 Deer Creek Road, MS 26U-4
Palo Alto, CA 94303-1392
rneff@labs.agilent.com

3150 Emerson Street
Palo Alto, CA 94306

Last modified February 23, 2000.