image of UC seal EECS247, Spring 1996

Analog-Digital Interfaces in VLSI Technology



  1. Instructor:
    P. R. Gray (pgray@eecs.berkeley.edu)
    506 Cory Hall 642-5179
    Office Hours: Wednesday 3-4, Thursday 1:30-2:30

  2. TA, Office Hours TBD

  3. Reader, Office Hours TBD

  4. Course Description
    This course covers many aspects of the design of integrated analog-digital interface electronics in CMOS and BiCMOS VLSI technology. Emphasis is placed on practical design aspects. Topics include transistor-level design consideration as will as block-level design. Representative system applications are also included.

  5. Prerequisites
    The primary prerequisite is EECS240 or equivalent. Exceptions must be by consent of instructor.
    EECS 242 is helpful, and a basic course in digital signal processing is very helpful.

  6. Textbook
    The required texts are:
    -- "Analog MOS Integrated Circuits, II," (editors Gray/Wooley/Broderson).
    This is an IEEE Press Reprint collection published in 1989,and is available at the bookstore.
    -- Course reader of reprint papers to be available about the third week of class.

    Suggested reference books are:
    -- For students who have not used HSPICE in earlier courses, a set of HSPICE manuals will be very helpful.
    These will be made available for purchase early in the semester.
    -- From time to time we will be using other simulators such as MATLAB.
    The manuals for these will be made available as needed.
    -- Gray and Meyer, "Analysis & Design of Analog Integrated Circuits," Third Edition, Wiley, 1993.

  7. Assignments
    There will be about 5 homework assignments spaced about one every week.
    In the second part of the course there will be a term project.

  8. Exams:
    There will be one midterm exam in approximately the eighth week.
    Your grade for the course will be made up approximately as follows:
    Homework, 20%; midterm exam, 20%; project, 30%; final exam, 30%

  9. Course Outline. Class notes.

    Table 1: EECS 247Y Course Outline, Spring 1996

    WeekTopicReading
    Jan. 15Introduction, A/D Conversion ConceptsMOS 3, 26, 159
    Jan. 22Sampling Concepts, S/H AmplifiersMOS 146, 153
    Jan. 29Voltage Comparators, D/A ConvertersMOS 119, 128, 370; R1,2,3,4,5
    Feb. 5Nyquist sampling ADCs - Serial and Successive Approximation (ISSCC Wed, Friday)MOS283, 357,R6
    Feb. 12Nyquist sampling ADCs- flash and multistep flashMOS331, R7
    Feb. 19Nyquist sampling ADCs- pipelinesMOS343, R8,9,10
    Feb. 26Self-calibration of Pipeline A/D converters R11,12,13
    March 4Oversampled ADCs- First and Second order sigma-deltaMOS 309, 324,324,R14,15,23
    March 11Oversampled ADCs- Higher order sigma-deltaR18,19,20,21,22
    March 18Continuous filtersMOS274, R24, R25
    March 25Spring Break
    April 1MOS Sampling Concepts, SC Filter DesignMOS159,223,231
    April 8SC Filters, Power, Speed limitsMOS 251,252
    April 15RF Analog Interfaces- ArchitecturesR26
    April 25Components of RF interfacesHandouts
    April 29Summary and representative applicationsHandouts

  10. Selected Readings, EECS 247Y, Spring 1996

    1. N. Kumazawa, et al, "An 8bit 150Mhz CMOS D/A Converter with 2Vp-p Wide Range Output," Digest of Papers, 1990 Symposium on VLSI Circuits, Kyoto, Japan.
    2. Groenveld, et al, "A Self-Calibration Technique for Monolithic High-Resolution D/A Convertters," IEEE Journal of Solid-State Circuits, Dec 1989.
    3. M. Pelgrom, "A 10b, 50Mhz CMOS D/A Converter with 75 Ohm Buffer," IEEE Journal of Solid-State Circuits, December 1990.
    4. D. Reynolds, "A 320MHz CMOS Triple 8-bit DAC with On-Chip PLL and Hardware Cursor," IEEE Journal of Solid-State Circuits, Dec 1994.
    5. H. Kohno, et al, "A 350MS.s 3.3V 8-bit CMOS D/A Converter using a Delayed Driving Scheme," Digest of Technical Papers, 1995 Custom Integrated Circuits Conference.
    6. M. de Witt, K.-S. Tan, R.K. Hester, "A Low-power 12-bi Analog-to-digital Converter with On-chip Precision Trimming," IEEE Journal of Solid-State Circuits, April 199
    7. T. Matsuura, et al, "An 8b, 20Mhz CMOS Half-Flash A/D Converter," Digest of Technical Papers, 1989 ISSCC.
    8. Kusomoto, et al, "A 10b, 20Mhz, 30mW Pipelined Interpolating CMOS ADC," Digest of Technical Papers, 1993 ISSCC.
    9. T. Cho and P.R. Gray, "A 10 bit, 20MS/sec, 35mW Pipeline ADC in 1.2 Micron CMOS," IEEE Journal of Solid-State Circuits, April 1995.
    10. Y.M. Lin, B. Kim, and P.R. Gray, "A 13bit 2.5Mhz Self-Calibrating Pipelined A/D Converter in 3 micron CMOS," IEEE Journal of Solid-State Circuits, April 1991.
    11. A.N. Karanicolas, H.-S. Lee, K.L. Barcrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE Journal of Solid-State Circuits, Dec. 1993.
    12. Cline, et al, "A 14-bit, 5Ms/sec Pipeline ADC in 1.2 Micron CMOS," 1995 CICC.
    13. B. Cho, D.W. Cline, C.S.G. Conroy, and P.R. Gray, "Design Considerations for High-Speed Low-Power Low-Voltage CMOS Analog-to-Digital Converters," Digest of Technical papers, 1994 Advanced Analog Integrated Circuit Symposium, Eindhoven, the Netherlands, March, 1994.
    14. J.C. Candy, G.C. Temes, "Oversampled Methods for A/D and D/A Conversion," IEEE Press Book forward.
    15. B.E. Boser and B.A. Wooley, "The Design of Sigma-Delta Modulation A/D Converters," IEEE Journal of Solid-State Circuits, Dec. 1988.
    16. K.C.-H. Chao, S. Nadeem, W.L. Lee, C.G. Sodini, "A higher order topology for interpolative modulators for oversampled A/D converters," IEEE Transactions on Circuits and Systems, March 1990.
    17. B.P. Brandt, B.A. Wooley, "A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion," IEEE Journal of Solid-State Circuits, Dec. 1991, vol. 26.
    18. B.P. Brandt, B.A. Wooley,"A low-power, area-efficient digital filter for decimation and interpolation," IEEE Journal of Solid-State Circuits, June 1994, vol. 29, (no.6):679-87.
    19. J. Fattaruso, et al, "Self-Calibration Techniques for a Second-order Multibit Sigma-Delta Modulator," IEEE Journal of Solid-State Circuits, Dec. 1993.
    20. R. Bair d, R. Fiez, "A 14-bit 500kHz Delta-Sigma ADC with 16 times Oversampling," Digest of Technical Papers, 1995 Custom Integrated Circuits Conference.
    21. P. van Gog, et al, "A Two-Channel 16b/18b Audio AD/DA Including Filter Function with 60/40mW Power Consumption," Digest of Technical papers, 1995 ISSCC.
    22. R. Baird and T. Fiez, "Linearity Enhancement of Multibit Sigma-Delta A/D and D/A Converters Using Data Weighted Averaging," IEEE Transactions on Circuits and Systems II, December 1995.
    23. Table of Contents, "Oversampled A/D and D/A Converters," IEEE Press Book.
    24. R. Schamumann, "Design of Continuous-Time Fully-Integrated Filters - A Review," IEEE Proceedings, August 1989.
    25. C. Laber, et al, "A 20Mhz Sixth-order BiCMOS Parasitic-Insensitive Continuous-time Filter and Second-Order Equalizer Optimized for Disk-Drive Read Channels," IEEE Journal of Solid-State Circuits, April, 1993.
    26. P.R. Gray, "Research opportunities in Low-power RF Integrated Circuits."
    27. Table of Contents, "Integrated Continuous-Time Filters," IEEE Press Book.