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Conclusion
This work attempted to design and build a prototype RF Power Amplifier that could be used in a system built to meet the DECT standard. A host of classes of RF Power Amplifiers was reviewed, as well as methods that could have been used to linearize the nonlinear classes of Power Amplifiers. A Class AB CMOS Power Amplifier was designed in a 0.6mm CMOS process that delivered greater than 250mW of peak output power with 31.1% efficiency in simulation.
The PA was implemented in a differential configuration, so as to minimize the amount of substrate current injected at the signal frequency, as well as to improve the dynamic range at the output and to increase the common-mode rejection of the circuit. The PA was designed in a CMOS process to allow it to be integrated on a single-chip with a full transmitter. The design used 3 stages to generate the power necessary; a Class A first stage, which controlled the output power level, followed by two Class AB stages to generate the final power level. The two Class AB stages used cascoded stages, both to reduce the Miller effect on the MOS gate-drain capacitance as well as to limit the voltage seen across the MOS oxide. Bondwire inductors were used as high-Q alternatives to on-chip spiral inductors, which is especially useful in minimizing the resistive loss in the inductors in the power stage.
A test board was also designed, which included all the necessary DC supplies as well as the RF matching components and the baluns necessary for the single-ended to differential conversion. Once the testing process was under way, a layout error was discovered. The AC coupling capacitors used between stages were poorly laid out, as these capacitors were not laid out to minimize the polysilicon series resistance. As a result, the testing process was unable to verify the actual working of the design.
However, the design process was valuable, in that much was learned about PA's in general as well as the method of designing a PA. While the results obtained in simulations were not verified, it is this author's opinion that a version of this chip with the layout of the AC coupling capacitors corrected would have verified the simulation results. Because of the difficulty of obtaining another run in the TSMC process, a second revision of this chip was not attempted, but, as stated, the process of designing the chip from start to finish was invaluable.
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