Class A

A Class A power amplifier (PA) is the simplest and most basic form of power amplifier. In Class A operation, the transistor is in its active region for the entire input cycle, and thus is always conducting current. As such, the device maintains the same gain (approximately) throughout the entire region, and in the case of a MOS device, is linear in that region. Figure 2 shows the basic Class A PA implementation, as well as some sample waveforms for a Class A PA.

Standard Class A Implementation and Waveforms

The problem with Class A structures however, is their inherently poor efficiency. As great as their linearity is, there is a question of whether or not it is worth the heavy price that must be paid in terms of efficiency. The device, since it is on (conducting) at all times, is constantly carrying current, and that current represents a continuous loss of power in the device. In this case, there is a great deal of power consumed (relative to the desired output power), over and beyond what is being used to drive the load. Ideally, the power consumed in the device should be zero, allowing all the power coming from the supply to be directed directly to the output. As a result, Class A tends to be used only in those situations where either the linearity requirements are so stringent as to necessitate an entirely linear output stage, or those in which the power consumption of the amplifier is less of an issue (for instance, when there is a "limitless" power supply, such as the outlet in the wall, from which to consume power).

The efficiency of a RF Class A PA is limited to 50%, and in FET implementations, the efficiency can never realistically reach 50%. In an ideal sense, where the output is biased at the supply voltage VDD, and the output swing has an amplitude of VDD, the efficiency is given by

,

where the term in the numerator is the power delivered to the load, and the term in the denominator is the average power delivered to the circuit by the power supply. In an inductor-less system, the efficiency is limited to 25% [3] , as the output voltage will not be able to rise above the supply voltage, and thus the swing will be constrained to VDD/2 and not VDD. However, note that in an FET case, it is not possible to have an output swing of VDD and still keep the device in saturation. As a result, the peak efficiency of an FET Class A PA implementation is significantly lower; PA's of this nature reported in the literature have an efficiency which is limited to on the order of 30% [6].

Class B

This next architecture in the area of power amplifiers involves taking a look at the active device that is driving the load, and realizing that there must be away to design that stage such that there is no standing current flowing, but the PA is still able to drive the load. In a class B structure, there are two devices, one which provides current to the load (pushes current into the load), and one which "removes" current from the load (pulls current from the load); possible circuit implementations are shown in Figure 3 .

Class B Implementations

This structure is usually called a "push-pull" structure. During the positive half of the signal swing, one device will pull current from the load, and during the negative half of the signal swing the other device will push current into the load, as indicated in Figure 4 . Another way of describing this condition is to say that the device conduction angle is 180 degrees, or one half the input cycle (with the full input cycle being taken as 360 degrees). When no signal is applied, however, there is no current flowing anywhere, as both devices are biased at their turn-on voltages. As a result, in an ideal case, any current through either device goes directly to the load, and thus attempts to maximize the efficiency.

This is also a generally linear class, although there is an instant (and possibly more, depending on the biasing) during each cycle when both devices are off, and this can produce distortion in the output. Known as crossover distortion, since it occurs when the signal is "crossing over" from passing through one device to the other device, this degrades the linearity of this architecture. Moreover, if different devices (i.e. NMOS and PMOS) are used for the push and pull devices, there will likely be a different transfer function from input to output depending on which device is on, which can degrade the linearity further. However, this architecture does allow for very high efficiencies, as in the ideal case the efficiency can approach 78% [3] , and thus this architecture can be useful in applications where the linearity requirements are a little less stringent. In practice, the efficiency of a Class B implementation may reach as high as 60% in GaAs implementations [7].

Class B Waveforms

Class AB

However, in situations where the linearity is still an important requirement, it would be nice to be able to utilize the push-pull concept and yet at the same time minimize the cross-over distortion that can cause problems in a class B structure. This idea is implemented in the Class AB structure, which, as its name implies, is a cross between a Class A and a Class B structure. The idea here is to use a push-pull structure, where each device is biased slightly above threshold. Circuit implementations of a Class AB PA are similar to those of the Class B architecture; what differs is the biasing and output waveforms. Examples of these are given in Figure 5 . This architecture is like Class A in that each device does carry current under nominal bias, but it is like Class B in that neither device is on for the entire cycle. By allowing the two devices to conduct current for a short period, the output voltage waveform during the crossover period can be smoothed out and thus can reduce the distortion at the output. Thus this structure can provide linearity close to a Class A structure with efficiency close to a class B structure. Depending on whether linearity or efficiency is the dominant metric, the bias point can be chosen to be close to the threshold (the Class B bias point), in which case both efficiency and linearity would approach the Class B levels, or it can be chosen such that the device remains on for most of the input cycle (closer to the Class A bias point), in which case the efficiency and linearity would start to approach the values of a Class A PA. Several Class AB PA's have been reported in the literature, with efficiencies ranging from anywhere between 30% and 60% [8] [9] [10] [11] .

Class AB Waveforms

Class C

A Class C Power Amplifier is the most basic of the non-linear Power Amplifiers used at RF frequencies. This architecture takes the idea of a Class B PA, where the device is biased at the edge of conduction, one step further in that it prescribes that the PA be biased below threshold. Equivalently, it is said that the device conduction angle for a Class C PA is less than 180 degrees. The appropriate voltage signal is applied to the device, and a portion of the positive input swing will take the device into the amplifying region, and thus the output current is a pulsed representation of the input. As a result of the pulsed nature of the output current, the input and output voltages are not linearly related, and as a result, the output of the PA will be highly distorted if the input voltage amplitude is changing. The desired effect of this method of operation is to minimize the current through the device when the voltage across the output is high, and minimize the voltage across the output when the current through the device is high, in order to minimize the power dissipated in the device (if at least one of the two quantities is zero at a given instant across the cycle of operation, then the power dissipated in the device is zero and all the power consumed is transmitted to the load). However, as a result of the nonlinearity, the Class C PA can only be used in a system with a constant-envelope modulation scheme (at least without any linearization, which will be discussed later in this chapter).

Class C Implementations and Waveforms

Another key requirement of an ideal Class C PA is the fact that the transistor is thought of as a current source, i.e. the current through the device should be independent of the voltage across the output terminals of the device (the drain and source in this case). This implies that the device should remain in its high gain region (forward active for bipolar junction transistors, saturation for FET's) while it is on. For a bipolar junction transistor (BJT), this simply means that the vBE of the transistor must remain greater than its vCE(SAT), usually around 0.2 V. This is not an overly stringent requirement, as it only decreases the possible output swing from the supply voltage VCC to VCC-0.2V. However, in the case of an MOS device, this requirement can be a significant limitation. The saturation region for a long-channel FET is nominally bounded by its input, i.e. the vDS of the device must be greater than its vGS -VT. However, as an inverting device, the vDS of the device decreases as the input voltage vGS increases, and as such, a limit is set on the maximum possible input voltage. This can unduly limit the amount of current swing, which can be especially important in a Silicon MOS environment, where the amount of transconductance the transistor provides is already low, and must be driven hard to generate large currents. One must be able to cope with either a low output voltage swing, so that a larger input swing can be supported, or a low drain current swing, so that the required input drive is small.

In Figure 6 , the standard configuration of a Class C PA as well as its mode of operation is demonstrated. The voltage waveform at the output is kept at the same frequency as the input by placing a tuned load at the output, ideally attenuating all the non-fundamental frequencies generated by the device. In an ideal case, the efficiency could be as high as 100%, if an ideal voltage waveform could be applied which only turned the device for an instant, and the corresponding instantaneous current was enough to generate the needed output power. Unfortunately, as this is not really possible, the efficiency of the device is less than 100% in the real case. However, the efficiency of the Class C PA can be 60% or higher, often much higher than seen in the linear case [12] [13].

Class F Implementation and Waveforms

Class F

Class F is mentioned here before Class E because Class F is really an extension of Class C. If you assume that a sinusoid is the input to the PA, then the amount of overlap between the non-zero current and voltage waveforms can be substantial and decrease the efficiency considerably. However, a significant advantage could be reached if the waveforms were square, and Class F PA's try to solve this by making the waveform at the output of the device more square. This is achieved by taking a Class C PA and placing an LC tank circuit tuned to the third harmonic frequency of the input in series between the device and fundamental-tuned output load, as shown in Figure 7 . The idea is that the device will see a non-zero load impedance for both the first and third harmonics, and thus the waveform at the output of the device will the sum of the first and third harmonics of the fundamental frequency, which make up the first two terms in the series expansion of a square wave. In this way, the output voltage waveform is closer to zero at the time when the current is flowing, decreasing the power lost through the device. The waveform at the output is still limited to the fundamental frequency, since the impedance at the actual output is tuned to the fundamental.

Class E

Class E PA's are fundamentally different than PA's based on the above architectures. In the previously described PA classes, the definitions of the specific architecture are given in low-level requirements (i.e. that the device should be biased above/below its threshold voltage, etc.). However, in a Class E PA, only circuit-independent signal guidelines are given, and the topology is not as constricted. In other words, the Class E PA must conform to guidelines that are more high-level in nature than the previous classes. In essence, the idea behind the Class E PA is to have non-overlapping output voltage and output current waveforms, and to limit the values of the voltage, current, and the derivative of the voltage with respect to time at the instants when the transition between non-zero currents and non-zero voltages and vice versa occurs.

The class E PA was originally designed for use in PA's which utilized devices with non-negligible turn-on and turn-off times, where the overlap between the output current and voltage waveforms was significant relative to the frequency of operation, enough so to cause unnecessary power to be consumed within the device. The ideas of zero-voltage switching, which are common in power supply converter and power supply regulator circuits, are used in this PA class [14].

Class E Implementation and Waveforms

The method used is to restrict the input waveforms and output waveforms, and ensure the non-overlapping nature of the two quantities, which entails (nominally) the creation of a load network which generates an "optimal" response. In the paper that first introduced Class E PA's, a large number of conditions were given as to the modes of operation of the device [14]. The first two conditions are the obvious ones, namely, that the device used in the PA should have minimal "on" voltage and "off" current (actually, the device "on" voltage and "off" current are prescribed to be zero). The next criterion states that the device should be completely off before the voltage across it changes, and that the device should be completely on before it starts to allow current to flow through it. Equivalently, this says that the current should be zero before the voltage across the device increases away from zero, and that the voltage across the device should return to zero before current is allowed to flow in the device. This allows for absolutely no power to be lost in the device independent of non-ideal switching times, since the circuit input and output are controlled such the device output voltage and current will never be concurrently non-zero. Thus their product, which represents the power lost in the device, is always zero, making the circuit 100% efficient.

There are several other criterion which need to be satisfied, most notable of which is the fact that not only should the device output voltage be zero before the current starts to flow in the device, but also that the time derivative of the voltage at the switching instant be zero as well. This ensures that if there is a deviation in the switching instant from the ideal switching time (when the output voltage is zero), the output voltage will be very small, and the power lost in the device due to this non-ideality will be relatively small [14]. With all these conditions satisfied, very high efficiencies can be achieved. However, until recently, Class E PA's have not really been feasible at PCS RF frequencies (several hundred megahertz and up), because of the size of the passive components needed in the standard Class-E output configurations. However, recent publications have indicated slightly different topologies, with more viable passive component sizes, especially for CMOS (where the large parasitic drain-bulk capacitance can cause problems in topologies that require small capacitances at the device output) [15].

There ends a brief discussion of the different classes of Power Amplifiers. More in-depth information can be found in some of the papers referenced in the previous sections, but unfortunately, a lot of information resides in the heads of PA designers in industry, and much of the knowledge used in PA design can be obtained only by talking with experienced designers and by working with them on PA design.

Cartesian Feedback

Cartesian Feedback takes the basic concept of negative feedback for linearization and applies it to the high-frequency PA realm. Applying negative feedback at high frequencies gives cause for worry, because while it can increase the linearity and the frequency of any poles that might exist, it will also reduce the forward gain of the amplifier. In the case of a CMOS PA, the device is being pushed to give as much gain as it possibly can, and thus any reduction in gain whatsoever is deleterious and undesirable.

Cartesian Feedback, however, avoids that problem by doing the negative feedback at low frequency. As a result, the RF PA appears as if it is operating in an open-loop manner, and to first order is not subject to the gain reduction that negative feedback can cause. The standard block diagram for Cartesian Feedback is shown in Figure 9 . As mentioned above, the linearization works around the entire transmitter, not just the PA, and thus is not direct linear feedback at the PA's operating frequency. As shown, the baseband digital bits are put through a D/A converter, the resulting signals (both I and Q channel) are put into a modulator, which combines the signals and upconverts them to the RF frequency (the exact method of conversion, i.e. direct conversion, heterodyne, etc., is not really important). The RF signal is amplified to the necessary power level from the PA. So far, this is a standard open-loop transmitter. At this point, an attenuated version of the RF PA output is demodulated, producing baseband analog versions of the non-linear PA's output, which are then subtracted from analog version of the digital bitstream sent to the PA. This method of linearization linearizes the PA signal within a small linearizing bandwidth bl, which is encompassed by a larger operating bandwidth bo. That is, the PA can linearize the signal for any band of size bl within the fixed band bo.

Cartesian feedback amplifiers in literature have been seen to provide as much as 50 dB of linearization; i.e., the magnitude of undesired spectral components adjacent to the desired signal, due to intermodulation, spectral regrowth, or other phenomena, has been reduced by 50 dB or more through this technique [16]. Several papers have also reported linearizing bandwidths on the order of several hundred kHz inside operating bandwidths of tens of MHz [16]. However, there are limitations to this technique. The linearization is only as good as the matching of both gain and phase between the upconverting modulator in the forward path and the downconverting modulator in the feedback path. Moreover, the stability of the loop must be guaranteed, which sets tight requirements on the loop gain and loop bandwidth [16]. Both of these affect the amount of linearization provided as well as the available linearizing bandwidth. Thus very tight control must be exerted over the components in the loop as well as the overall performance of the loop.

Cartesian Feedback Architecture

Predistortion and Adaptive Predistortion

The Predistortion method of linearization is similar to the cartesian feedback method, in that it looks to modify the signal at the input of the PA, but moves the linearization one step back in the transmitter chain. The Predistortion method makes use of a DSP by storing known predistortion coefficients in a lookup table (LUT), which are then used to predistort the input digital bitstream to create a signal that will generate a linear representation of the desired input. The coefficients are generated based on the known distortion characteristics of the PA. Adaptive Predistortion takes this notion one step further in that it periodically senses the PA's output in order to update the coefficients in the DSP for any time-varying non-linearities in the forward path. Because the feedback loop is only closed at selective times, the linearized transmitter is essentially open-loop and can be viewed as unconditionally stable [17]. This method can be useful when the system already incorporates a DSP, which may remain unused or partially unused in this transmit time.

The basic structure of a Predistortion implementation can be seen in Figure 10 . It can be seen that this method is somewhat similar to the Cartesian Feedback method mentioned in the last section when in its adaptation mode, but that the signal fed back is converted to a digital representation using an A/D converter and compared to the input bitstream in order to update its predistortion coefficients. While the linearization is not being adapted, the transmitter is strictly open-loop, and thus stability is not an issue. The digital I and Q channel bits are combined in order to generate the value used to index the lookup table; the methods of combination can include using both the I and Q bits in order to generate an exact 1-to-1 mapping between the digital complex plane and the RF output plane, or possibly combining the I and Q bits to generate and effective signal magnitude [19]. The latter can give a significantly smaller LUT.

Practical considerations can set bounds on the amount of linearization attained through this method. The amount of linearization can be limited by the sampling frequency of the digital input bits. The linearizing bandwidth should nominally be limited by the sampling frequency of the input, due to the Nyquist Sampling criterion. Reduction of the sampling frequency can cause limited linearization in higher order products, with the linearizing bandwidth decreasing as the sampling rate is decreased [19]. Moreover, when the feedback loop is active for coefficient adaptation, extremely tight control must be maintained in order to ensure correct adaptation. Clearly, since this feedback is periodic and not continuous like in the Cartesian Feedback (CF) case, the amount of errors in the adaptation loop introduced by the loop components will be reflected directly in the updated coefficients.

Digital Predistortion Architecture

Again, these techniques have demonstrated reduction in IM components by more than 50 dB for the systems in which they were implemented [17] [19]. However, one other significant drawback of this technique is that a DSP is needed for this linearization scheme, which can significantly add to the total power consumption of the transmitter. Remember that any extra power spent to linearize the PA directly reduced the effective efficiency of the PA; none of the extra power consumption goes to the load. This reduction in efficiency may or may not be allowable in a given system or a given implementation, and this must be considered when implementing the transmit path.

Feed Forward

This method does not use feedback; as the name implies, it uses a feed-forward technique in order to linearize the PA output. The block diagram of the Feed Forward method is shown in Figure 11 [18]. As shown, the RF input is split into two paths. The first path contains the nonlinear power amplifier which is to be linearized. The nonlinear amplified signal is then tapped for an attenuated version of its output and subtracted from a delayed version of the original RF input. Since the RF input contains only the desired signal, whereas the attenuated version contains the desired signal as well as other harmonics due to the nonlinear nature of the PA, the difference contains only the unwanted harmonics, at least in an ideal sense. This is shown in Figure 11 . The difference is then amplified using a linear PA, which is then subtracted from a delayed version of the PA output. The linear PA ideally does not add any extra frequency components to its input, and thus when it is subtracted from the original PA output, it ideally cancels the nonlinearities in the first PA's output, and thus the final output is a linear representation of the input.

Feed Forward Architecture

While the Feed Forward technique is completely open-loop and thus never suffers from any stability concerns, the matching between the two paths is of critical importance. The artificial delay added to the lower path to compensate for the delay through the RF PA (as shown in Figure 11 ) must closely match the delay introduced by the RF PA; otherwise, the subtraction will not accurately cancel the linear terms in order to generate the error signal. Similarly, the delay introduced into the upper path in order to compensate for the delay through the linear PA used to amplify the error signal must match that delay. Mismatch in that delay can cause poor distortion cancellation, since the combiner will combine two signals that are effectively out of phase, possibly increasing the phase distortion.

Moreover, efficiency degradations can be problematic in this case, as they were with Adaptive Predistortion. A linear PA is needed in the error path of the Feed Forward technique. One of the reasons to use a nonlinear PA in the first place (which thus required the investigation of linearization techniques) was the better efficiency of the nonlinear PA. The Feed Forward technique re-introduces a linear PA into the signal path. It must be noted, however, that using a linear PA to amplify the error signal does not have to consume as much power as using that same linear PA as the PA used to amplify the RF input. The power level at the output of the linear PA in the Feed Forward case is only that required to adequately cancel the error components in the output, which need not require the amount of amplification (and thus power consumption) of the original input signal. That is, the error signal may only need to be amplified to a small fraction of the output peak power in order to sufficiently reduce the error components, and thus the power consumed in the linear PA may be small. That being said, however, it must be remembered that 100% of that power detracts from the overall effective efficiency of the PA, and thus the amount of power "wasted" there must be carefully monitored.

Even with these drawbacks, the Feed Forward technique can be very valuable. The literature has indicated linearization of up to 60 dB in a high power system [18] , which can be very useful. This technique can be especially significant in a base station-type application, or one where there is an essentially infinite power supply available.

DECT Frequency Allocation

The DECT standards specifies that communications will be done in a frequency band with a width of 17MHz centered at approximately 1.89GHz, making it a narrowband communications system. The band consists of 10 channels, each of width 1.728 MHz, but with a data rate inside the channel of 1.152MHz. Each channel is furthermore divided into 12 different time slots, each of those carrying the communications traffic of a different user. The basic frequency bands are shown in Figure 12 . The power output levels in DECT vary from approximately 19 dBm, or 80 mW, all the way to 24 dBm, or 250 mW [20].

The transmitted power time-domain mask is shown in Figure 13 [20]. The output power must ramp up from its essentially zero value while the device is not transmitting to its final value in a short time. Moreover, once at the transmit frequency, the power should not deviate from the desired value. Finally, the ramp down is just as critical as the ramp up, indicated by the amount of time in which the power must return to its off-state minimum value.

DECT Transmit Power Time-Domain Mask

These are the specifications of the DECT standard that are relevant to the design of the power amplifier.

Ideal Effect of Tuning on Gain vs. Bandwidth

Equally important, though, is the fact that creating a resonant structure decreases the amount of current that is needed to drive the large capacitances inherent in large driver stages. A parallel resonant structure needs only to be supplied with an amount of current that is less than the circulating current in the resonant structure by the quality factor, or Q. The Q is a ratio which compares the imaginary parts of the impedance to the real parts of the impedance, in order to determine how lossy an element is. Thus the higher the Q of an element is, the lower its resistive component is, and the less power that is lost through dissipation through the real part of the impedance. For an ideal LC parallel resonant circuit, with infinite Q, no current needs to be supplied by an external force, as the structure will resonate with any initial excitation. However, for non-infinite Q's, the circuit will lose some of the circulating current due to losses in the resistive components of the circuit. For example, if the inductor is non-ideal, and has a finite Q due to a parasitic resistance in series with the inductor, the current circulating will eventually dissipate, and will need to be replenished. Since the amount of current that needs to replenished is less than the total needed to drive the capacitor, there is a possible power savings because of the inductor, and a second benefit is derived.

Reduction in swing requirements due to Differential Configuration

One way to attempt to solve this problem is to use a differential architecture. The differential design allows for more dynamic range in the circuit, as the voltage swing requirements at every node in the circuit are essentially cut in half. For example, if an eight volt peak-to-peak (pp) swing is required at the output, a single-ended implementation would need to support the entire eight volts at its output node vOUT. However, a differential implementation, in which the output is connected across the two differential output nodes, would require that each output node only support half of the desired output swing, with the difference between the two providing the required total voltage. This is illustrated in Figure 15 .

Another benefit of a differential architecture is the immunity to common-mode (CM) noise and other disturbances. The final stage of a PA implementation will often be generating large amounts of AC substrate current, which could cause havoc with a single-ended implementation, due to fluctuations in substrate voltage, or more generally as large external noise that could cause the circuit to malfunction. However, in a differential implementation, that noise, which can be considered to be CM signals, can really be ignored for all intents and purposes.

Transistor Configuration in the Output Driver Stage

The stage of the PA that actually drives the antenna is often called the power stage, or the driver stage. This stage needs to be designed first, as the rest of the design, including the pre-amplification stages as well as the passive elements, depends on the particulars of this power stage. Moreover, the specifics of this final stage depend only on already known quantities.

Basic Differential Implementation

This stage must, with the available input drive, be able to drive the output load with the required current, such that the output power is produced. The most basic amplifier that can be used in this case is a single transistor amplifier, which in this case can be implemented as a simple common source stage. In Chapter Three, a differential design was proposed, and thus the most basic differential output stage is shown in Figure 16 . This is nominally a simple differential pair; the only thing missing is the constant tail current. This tail current is not included because of the large standby power dissipation that would result. In this particular case, in order to generate 250 mW of output power, as required by the DECT standard, a 100 mA peak sinusoidal current is needed through a 50W load. In order to maintain the above circuit with a tail current, the size of the tail current would have to be that 100 mA, plus whatever extra current is needed to drive all the capacitances at the output, as well as any excess current needed to keep the devices saturated throughout the entire cycle of voltage excursions. This means that independent of the size of the input signal, the amount of current drained from the supply would be that necessary to drive the maximum output power load, and thus even for the small output power level situations, the current drain on the battery would be close to the maximum. Instead, the tail current was eliminated, and the devices were biased just above threshold, to minimize the DC current taken from the supply. Moreover, this makes the AC current signal dependent, and thus the amount of current taken from the supply for the instances when the output power level is lower than peak can be significantly less than that for the peak output power case.

While the above circuit implementation is nice in its simplicity, it does suffer from one significant problem, and that is the problem of the input capacitance the previous stage will see. The common source amplifier suffers from the Miller effect, which makes the input capacitance seem significantly larger than just the physical Cgs of the device due to the different voltage swings at the two terminals of the parasitic feedback capacitance Cgd. As a result, both the Q factor as well as the impedance level of the input impedance to this power stage are reduced. Simulations indicated that the increase in the input capacitance was significant enough that other avenues needed to explored. While tuning that input capacitance with an inductor would ideally seem to solve the problem, the overall lowered Q factor of the tuned circuit, as well as the lowered impedance level, would require more current from the supply to drive the imperfect LC tank.

Cascode Differential Implementation

The first and most obvious answer to solving the problem of the Miller capacitance is to use a cascode, which has a differential structure as shown in Figure 17 . The cascode minimizes the effect of the Miller capacitance by forcing no amplification at the output node of the lower device's Cgd, thus diminishing the Miller effect. The cascode also nominally can give better gain from its input to its output because of an increase in the output resistance of the device.

Another key advantage of the cascode, especially in these high-frequency, high-power stages is that the cascode provides nice reverse isolation between its output and its input. If there were to be any significant amounts of feedback between the input and output of the feedback stage, it would be quite possible for the power stage to go unstable. A common metric in the stability of high-power PA's is the stability factor k, which is defined as

for absolute stability [4] , where

.

In conventional microwave designs, a discrete device, often a GaAs MESFET device, is thoroughly characterized to determine its large-signal S parameters, which can then be used in determining the PA's stability using See . However, in the realm of integrated CMOS PA design, such luxuries are not available to the designer; as such, a different method to guarantee stability must be examined.

In a standard, single MOS device amplification stage, the output signal can be fed back to the input by the gate-to-drain capacitance Cgd. At high frequencies, the impedance of this capacitance decreases, and more and more of the output will be fed back to the input. The cascode, on the other hand, has no such connection, and thus provides larger amounts of reverse isolation. Really, the only method of feedback to the input to the final stage is through parasitic interconnect capacitance, which can be minimized through good layout practices, reducing the possibility of instability due to feedback by keeping the amplifier an open-loop system. The stability of the amplifier can and will be verified in SPICE simulations before sending it for fabrication.

The cascode is not without its drawbacks, however. In general, in order to have high power at the output, high voltage swings, high current swings, or both are required. The amount of voltage swing or current swing is determined by the output power and the optimum resistance. For a sinusoidal output,

or

Ideally, the load resistance Ropt seen by the stage should be as close to the actual value of the component at the output (in this case, the antenna) as possible, in order to minimize the losses due to the necessary impedance transformation between the load and the device. The stacking of devices in a cascode limits the output voltage swing that is available, especially if the goal is to keep the devices in the saturation region (for MOS devices). If the output voltage swing is limited, then the current swing must be increased (and the optimum resistance decreased) in order to achieve the same power. Not only does the reduction in the optimum resistance decrease the efficiency, due to the now-required impedance transformation at the output, but the increased current requirement increases the amount of capacitance seen at the output. The larger capacitance at the output requires more current to drive it, requiring a larger device to generate the current. As a result, if the voltage swing at the output is limited, it can decrease the efficiency, as it requires more current to be drawn from the supply to drive this larger capacitance; this current is not directly driving the load, and directly reduces the efficiency. Thus the cascode can cause complications in the design of the output.

Optimum Load Resistance Determination

The next key step in the design of the output stage is the determination of the load resistance, which is dependent on the available voltage swing at the output. In an RF or microwave system, the terminal impedances are all normally designed to be 50 W by convention. The purpose of the PA is to drive the antenna, which is nominally modeled as a 50 W resistor. However, there is no guarantee that there will be enough voltage swing available to drive the antenna with the desired output power. For example, if the available voltage swing is 3V peak and the load resistance is 50 W, then the power delivered to the load at the RF frequency will be given by applying See

,

which is not the 250 mW desired in this application.

This then requires that some conversion must take place between the PA output and the antenna so that the desired power level can be obtained at the antenna. A common and simple way of doing this is to use an impedance transformation to transform the impedance of the antenna to a value consistent with the available voltage swing and desired output power. This transformation network is usually a network of passive, (ideally) lossless components, usually capacitors and inductors. The transformation network, being lossless, will deliver the same amount of power to the antenna as the PA delivered to it. In the case where there is a limited voltage swing and the desired peak power cannot be achieved with the real load, the optimum resistance will be reduced below that value. In this case, effectively, voltage has been traded for current, and the required power is achievable, even with the voltage limitations.

In the original design specification, the goal of this research was to design the PA so that it would operate under a 3V supply voltage. In this design, the output of each stage is biased at the power supply voltage by an inductor. For a power supply voltage of 3V, which was one of the design goals, the voltage swing was limited to between 1.8V and 2V peak, in order to keep the bottom device in the saturation region. According to See , the optimum load impedance is

.

However, in order to keep the design simple, it was desired to try to keep the optimum resistance as close to 50 W as possible. In order to accomplish this, the power supply for the final stage was raised to 5V, giving ample headroom to allow the output node of each side of the differential configuration to drive 250 mW or more into the 50 W load.

Device sizing requirements

Now that the transistor configuration has been decided, the output stage has to meet the required peak output power level. Using See , the peak current swing needed for 250 mW of output power is

,

at the fundamental frequency (equivalent to 5V peak sinusoidal voltage). In order to obtain this current, the output devices must be large enough to sink that peak current, as well as any bias current and the current needed to drive the other passive components for the given input signal at the RF fundamental frequency. The amount of current needed to drive the other components is highly dependent on the output voltage swing (which is nominally fixed), the Q factor of the passive network (again, fixed).

In this case, a 100 mA sinusoidal current must be supported through the load. A key point to note when sizing the devices is that the peak current for a given voltage is different in the DC and AC cases. The device must be sized so that it can provide the required current under the AC condition; thus when characterizing the device, the peak current for a given voltage at the input must be evaluated at the frequency of interest, or in this case, 1.9 GHz. For this application, the final sizes of the 4 devices in the output stage was 3000mm by 0.6mm.

Structure of Passive Components in the Output Stage

Once the transistor configuration has been decided, the structure of the passive components that make up the rest of the final stage must be designed. The purpose of the passive components at the output is twofold: first, the imaginary part of the output impedance at the desired output frequency must be canceled. This is done to ensure that a solely resistive load is seen and all the output signal at the fundamental frequency is converted into real power; imaginary power at the output is wasted. Second, the passive components must, if necessary, transform the resistance of the load into the optimum resistance for this particular Power Amplifier (PA) application.

In order to maximize the voltage swing at the output, the drain must be biased at a high DC voltage. Standard practice in RF PA's is to bias the output node of the transistor (or the cascode, in this case) at the power supply VDD through an inductor, often an RF Choke for AC isolation at the frequencies of interest.

The cancellation of the imaginary portion of the transistor's output impedance can be done very simply. The imaginary portion of that impedance usually derives from the output capacitance of the transistor and any other stray capacitances, possibly due to output interconnect. The simplest way to cancel that imaginary capacitance is to use an inductor to create a resonance at the fundamental frequency of operation, which was the method used here. However, this method does not account for the nonlinearity in the device output capacitance, which results from the voltage-dependent drain-bulk junction capacitance of the output node. As the output voltage changes, the output capacitance changes as well, and as a result, the imaginary part of the total impedance (including the inductor used to resonate the capacitance) will vary from the ideal. This can give a large capacitive range to match; one solution is to match the inductance to the average value of the capacitance across the output cycle, which is what was done here. This minimizes the deviation from the resonance of the tuned circuit as the capacitance traverses its range of values.

The output stage, including both the RF Choke as well as the impedance matching inductance, is shown in Figure 18 (a), and the equivalent AC circuit is shown in Figure 18 (b). The RF Choke is an off-chip, large inductance that acts as a DC short circuit and an effective AC open circuit at the RF frequency relative to the other impedances in the circuit. As stated in Chapter 3, the impedance matching inductors are implemented using bond wire inductances, to take advantage of the high Q properties of bond wires.

Final Output Stage Configuration

Biasing

Another important issue in the design is the issue of biasing. This final stage will be biased just above threshold, as the choice of the Class AB topology mandates. However, as described in the next section, the previous stage will be inductively loaded, and thus the two stages can not be seamlessly connected; the two stages must be AC coupled. This is most easily done through a coupling capacitor. However, the capacitor must be large enough that there is no significant loss of signal across the coupling capacitor due to the voltage division between the coupling capacitor and the gate capacitance of the final stage. Moreover, the parasitic bottom plate capacitance of the coupling cap will increase the effective gate capacitance of the final stage, causing more signal loss across the AC coupling capacitance. In order to achieve a balance between signal loss and chip area (as the capacitor size increases, so does the area required to implement it), a coupling cap value of 20 pF was used.

The actual DC biasing of the stages was done through an off-chip bias; as this design was a first attempt at design an integrated PA, this allowed the bias voltage of each stage to be controlled in order to choose the optimum point (in case the bias points chosen in the design process were not optimum). In essence, it allowed for some more degrees of freedom in optimizing the design at the testing stage, and would return more information in order to better tune the design loop.

Second Stage of PA

Finally, a similar approach was used to design the first stage of the PA, and this gave the size of the first stage to be 60 mm by 0.6 mm. The first stage design is shown in Figure 20 .

First stage of PA

The first stage is also used for another key function, and that is for controlling the output power level. As stated in Chapter 3, the output power level needs to be controlled over a wide range. In order to accomplish this power control, the first stage is designed to be a Class A stage. It is simply a differential pair fed by a tail current source, which has a controllable value in order to control the gain through the first stage. As the current is increased, so is the gain in the first stage and equivalently the gain through the PA, modulating the amount of power delivered to the antenna. This is a relatively simple scheme for power control, which can easily be implemented by a current DAC, allowing digital control of the output power. For this implementation, however, the current source used was implemented off-chip, in order to allow a wide range of available currents to be supplied to the input differential pair. In the case that the actual chip operation differs from the simulation results, the tail current of the first stage could be varied over a large range in order to optimize the performance of the PA. Simulation results of the PA will be presented after the discussion of the layout, as the extra parasitic capacitances that the layout introduces into the PA affected the values of the inductors used in the design.

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This becomes exceedingly important as the device size grows, as the Q of the capacitor will dominate the overall Q of the network; using bond wires to raise the Q of the inductors is pointless if the capacitor Q is allowed to become inordinately small. For smaller devices, such as those in the first two stages of this design, this is less of a concern, as the entire device can be laid out in a small area, which inherently limits the distance to the substrate contact. However, for the final stage, the final devices are large enough that even if the device is parallelized in order to reduce the gate RC time constant, as indicated earlier, the device must be broken up even further so that substrate contacts can be interspersed in between sub-blocks of the overall transistor.

Practically, the maximum width of a single finger of the fingered (or comb) MOS device structure was limited to about 20m/0.6m in this process, in order to keep the device a good distance away from the point where the gate RC time constant was a problem. This safe distance was calculated to be at least an order of magnitude less than the period of interest of the signals, or less than approximately 50 ps. Also, the large final stage devices, which were earlier calculated to be 3000m/0.6m in size, were split into four separate banks of devices, with each bank surrounded by a sea of substrate contacts to capture all the AC substrate current. The layout of the output stage can be seen in Figure 21 .

Layout of Output Stage Devices

Layout of First Stage Transistors and First Stage Bond Pads

The second stage transistors were laid out in similar fashion to those in the first stage, as shown in. The transistors are still relatively small. Note again that the multi-finger device is surrounded by substrate contacts. As the devices, as well as the currents they carry become larger, the amount of substrate current grows as well, requiring more and more contacts to help keep the substrate quiet.

Second Stage Device Layout

Final Circuit Schematic