The Design Of A 1.9GHz 250mW CMOS Power Amplifier For DECT
This report details the design process of a RF CMOS Power Amplifier (PA) designed in a standard CMOS process. The Power Amplifier was designed for the Digital European Cordless Telephone (DECT) Standard, which has a transmit frequency of 1.9 GHz and requires a peak output power of 250mW. The process of designing this PA required a survey of different methods of PA implementation, after which a CMOS PA was designed. We designed a differential Class AB CMOS PA in a 0.6mm standard CMOS process which could generate 250mW of output power into a 50W load. The design utilized high-Q bondwires as tuning elements and utilized a cascode structure in order to reduce the effective capacitance seen in the circuit and to reduce the voltage stress on the gate oxide. The circuit was designed and layout was completed, and post-layout simulations indicated a peak efficiency of 31.1% in the PA.
There are many people whom I would like to acknowledge for their assistance and support in completing this work, both technical support and advice as well as moral support.
First and foremost, I'd like to thank Professor Paul R. Gray for his guidance and insight, and also for his patience in seeing this work through. The bulk of the work related to this report was completed by the summer of 1996, and yet due to outside factors, the report was not completely written until now. Professor Gray's patience in this matter was greatly appreciated. I'd also like to thank Professor Robert Meyer for his help in answering questions I had along the way.
Thereare many students whose help was invaluable during the course of this work, both for their assistance with the technical aspects of this research as well as their friendship and support throughout. They include (but are not limited to) Lapoe Lynn, Kevin Stone, Andy Abo, Keith Onodera, Srenik Mehta, Chris Rudell, Tony Stratakos, Jeff Ou, Jeff Weldon, Carol Barrett, Todd Weigandt, Priya Viswanath, Dave Lidsky, Tom Burd and Dennis Yee. This work was heavily dependent on their technical contributions as well as their non-technical assistance. Several of the graduate students who were senior students when I started and who have since left were also of great assistance in their own ways, including Greg Uehara, Cormac Conroy, and Ken Nishimura. I would also like to thank Vikram and Dipanwita Amar for their support of all my pursuits during this time.
I most certainly could not have come this far without the assistance of my parents and my sister Kala. They have been extremely important not only in making me who I am, but also in helping me through the highs and lows that have accompanied not only this graduate school effort, but all my ambitions and pursuits.
This work was funded by NSF and the Department of Defense (through the National Defense Science and Engineering (NDSEG) Fellowship).
1.1 Architecture of an RF System 1
2.2.1 Linear classes of Power Amplifiers 8
2.2.2 Non-linear classes of Power Amplifiers 13
2.2.3 Linearization Methods 19
2.2.3.2 Predistortion and Adaptive Predistortion 21
Chapter 3: Design Goals and Approach 26
3.3.4 Differential Topology 34
3.3.6 Chip-On-Board (COB) Die Attachment 36
4.2.1.1 Transistor Configuration in the Output Driver Stage 38
4.2.1.2 Optimum Load Resistance Determination 42
4.2.1.3 Device sizing requirements 44
4.2.1.4 Structure of Passive Components in the Output Stage 44
4.2.2 Pre-amplification stages 47
4.3.3 Other Layout Issues and Solutions 52
Chapter 5: PC Board Design and Chip Testing 62