The recent boom in the portable wireless communications market has
created a need for low-power, low-cost implementations of wireless
communications devices, such as cellular phones.  One of the most
challenging blocks in the cell phone is the radio transceiver.  A key
component of the radio is the Radio Frequency (RF) Power Amplifier
(PA), which transmits the data from the mobile communications device
to the receiving station.  The goal of this research is to find ways
to use standard CMOS VLSI technologies, which are relatively low-cost
technologies compared to conventional Gallium Arsenide, to implement
RF PAs up to 1.9 Ghz and power levels of 30 milliwatts to 1 watt with
50% efficiency or more for battery-powered PCS applications. Earlier
work on CMOS implementations has focused mainly on significantly lower
power levels[1] or lower transmit frequencies[2] and has not managed
to maintain high efficiencies over the entire power range.

To that end, two PAs are being designed: a 1.75GHz, 1W PA as well as a
1.9GHz, 250mW PA, both in a 0.35um CMOS technology.  Both PAs being
designed are designed to operate as Class C PAs, which refers to that
class of PAs which generate a pulsed output current, and limits the
portion of each cycle for which both output voltage and output current
are non-zero. This limits the power consumed in the device, allowing
for higher PA efficiencies.  Class C PAs are non-linear, and thus this
style of PA can only be used in systems using a constant-envelope
modulation scheme, such as GSM or DECT.  This implementation uses both
on-chip spiral inductors as well as bond-wire inductors in order to
create the tuned inter-stage loads needed to maximize gain as well as
the output matching network needed to maximize the power transfer and
minimize reflections.  A peak output power on the order of 1W is
achieved with an efficiency of nearly 50%, according to simulations.
The implementation of the 1W PA has already been fabricated and is
currently being tested for performance.  The 250mW PA is currently
being designed, and will be integrated, along with the 1W PA, into a
combined DECT/GSM integrated transceiver chip.

The larger goal of this research is not only to demonstrate the
feasibility of RF transmit amplifiers in CMOS but also to try to
identify a general design methodology that will help in future PA
designs.  Power Amplifiers are still, in general, designed using an
empirical process, in which the devices to be used are fully
characterized before much of the design process can proceed.  Our goal
is to develop a Class C PA design methodology using standard device
models, such as SPICE models, without requiring extensive RF device
characterization.  The method being proposed in this work is to use a
simplified, piecewise transistor model, and generate a piecewise
approximation to the output current waveform.  Using simple
mathematical models, important design parameters such as efficiency or
harmonic distortion can be predicted without the use of heavy computer
simulations or without the need for heavy characterizations of the
device.  So given a particular set of desired performance criteria,
design paramaters such as the input bias level, input amplitude, and
device sizes can be optimized to reach an approximate design in a
reasonably short amount of time.  Currently, output predictions of the
output amplitude and efficiency have been generated which closely
match HSPICE simulations, and the testing of the experimental
prototype will further provide important feedback in the development
of the design methodology.  This information will assist in both
design and performance prediction based on PA Class and process
technology.

[1].  A. Abidi, et al, "The Future of CMOS Wireless Transceivers",
International Solid-State Circuits Conference Digest of Papers, San
Francisco, CA, February 1997, pp 118-9.

[2]. D. Su and W. McFarland, "A 2.5V, 1W Monolithic CMOS RF Power
Amplifier", Proc. IEEE Custom Integrated Circuits Conference, Santa
Clara, CA, May 1997, pp. 189-92.