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Coping with the floating-body effect in SOI DRAM
Troy Robinson and Alejandro Flores
Abstract:
Giga-bit scale DRAM require both reduced size in the basic cell and a longer refresh time in order to maintain power consumption. Therefore, latency time increases and leakage becomes a major concern. SOI technology is a strong candidate for giga-scale DRAM as long as the major drawback of floating body effect is solved. Reduced capacitances in SOI with respect to bulk, improves the subthreshold swing and performance of circuits. Nevertheless the absence of a body contact leads to data degradation [1]. The following proposal will investigate the Boosted-Sense Ground configuration as a solution.
Floating-body effect
The body potential of an SOI transistor depends on its biasing history and the generation and recombination mechanisms. Let us consider an NMOSFET as the one-T memory cell. The worst case regarding data corruption is when the one-T cell has been accessed to store a 1. If the cell is kept with the word line low and the bit-line high until , the body reaches a steady-state because of the thermally-generated holes (this period is known as the latency time). When bit-line is pulled down when accessing other cells tied to the same line, the parasitic npn BJT is turned on and leakage occur, leading to persistent degradation of the value stored: the source-body energy barrier is reduced and holes are injected into the source diffusion (acting as the emitter in the parasitic BJT) and electrons from the source into the body, which are then collected by the drain (or collector). If the process is repeated, the storage capacitor can be finally discharged. This problem has been analyzed in [2] and modelled in the SOISPICE software [3].
Boosted-Sense Ground
The boosted-sense Ground was proposed in [4] as a solution for high latency 256M memories. the basic concept is to avoid the turning on of the parasitic BJT by forcing the Base-Emitter pn junction to remain reverse-biased even when the body is charged up. In fact, the same idea underlies if we use the MOSFET terminology: charging up of the body lowers the threshold voltage and to keep the transistor off, gate-to-source voltage has to be further reduced. this can be done either by lowering the word-line off voltage below zero or rising the low level in the bit-line. [2] shows an optimum voltage around 0.4V to keep the leakage at a minimum. The BSG solution was proved to be functional for bulk technology [4]. We plan to investigate the feasability of the BSG approach (also proposed in [5]) and its further implications in the memory performance and power consumption.
Other solutions.
As stated, other solutions have been proposed to overcome the floating body. Some of them are creating an extra connection[2], adding a thin silicon connection linking the body of all transistors on a die [6] or rising the threshold voltage of the transistor forming the cell. We believe that the most promising alternative seems to be the cold CMOS solution: since holes in the body are thermally generated, cooling down the devices to low temperatures solves the floating body problem. This would mean a change in the complete architecture to take advantage of the low T environment, such as combining CMOS with Superconducting technologies.
Conclusion
In this proposal we have motivated the need for analyzing the SOI DRAMs as an alternative for giga-bit scale memories. The main problem is the floating body effect, which can corrupt stored data. The BSG solution seems to be a good fitting alternative and its impact on the system performance should be investigate. Other alternatives include the cold CMOS approach which would lead to other benefits of combining superconducting technologies.
References
[1] M. Pelella et al. 1995 IEEE SOI Conf Dig. pp.8-9
[2] J.A. Mandelman et al. 1996 SOI IEEE SOI Conf. Dig. pp. 136-137
[3] D. Suh et al. IEEE Electron Device Letters, vol. 17 Aug. 1996 pp. 385-387
[4] M. Asakura et al. IEEE JSSC, vol 29, nov 1994, pp1303-9
[5] Y. Yamaguchi et al. 1995 IEEE SOI Conf. Dig. pp 122-124
[6] W. Chen, et al. 1996 VLSI Symp. pp 92-3
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